Re: [PATCH v2] cpufreq: intel_pstate: Add Icelake servers support in no-HWP mode
From: Doug Smythies <hidden>
Date: 2021-09-07 20:16:24
Also in:
lkml
Hi Srinivas, Thank you for your reply. On Tue, Sep 7, 2021 at 9:01 AM Srinivas Pandruvada [off-list ref] wrote:
On Tue, 2021-09-07 at 08:45 -0700, Doug Smythies wrote:quoted
Recent ASUS BIOS updates have changed the default system response for this old thread, rendering "intel_pstate=no_hwp" useless. It also raises a question: If BIOS has forced HWP, then how do we prevent the acpi-cpufreq driver from being used? Read on.Does BIOS has option to enable Intel speed shift with no legacy support? Then this option will not populate ACPI _PSS table.
The option is there no matter what. I have tried every variation of legacy or no legacy that I can find. Currently: Current boot mode: UEFI Firmware mode SecureBoot: disabled
quoted
On Fri, May 14, 2021 at 3:12 PM Doug Smythies [off-list ref] wrote:quoted
On Fri, May 14, 2021 at 1:33 PM Giovanni Gherdovich < ggherdovich@suse.cz> wrote:quoted
On Fri, 2021-05-14 at 08:31 -0700, Doug Smythies wrote:...quoted
quoted
...
quoted
Previous correspondence was with BIOS version 1003. There have been 3 BIOS releases since then (at least that I know of), 2103, 2201, 2301, and all of them have changed the behaviour of the "Auto" setting for Intel Speed Shift Technology BIOS setting, forcing it on upon transfer of control to the OS. Where with "intel_pstate=no_hwp" one used to get 0 for MSR_PM_ENABLE (0x770) they now get 1.So they are forcing Out of band OOB mode. Does bit 8 or 18 in MSR 0x1aa is set?
No.
Here is the output from my msr reader/decoder program.
Kernel 5.14 (unpatched).
intel_pstate=disable
BIOS setting "Auto" for Intel Speed Shift,
Driver: acpi-cpufreq
doug@s19:~$ sudo c/msr-decoder
How many CPUs?: 12
8.) 0x198: IA32_PERF_STATUS : CPU 0-11 : 45 : 45 : 45 : 45 :
45 : 45 : 45 : 45 : 45 : 45 : 45 : 45 :
B.) 0x770: IA32_PM_ENABLE: 1 : HWP enable
1.) 0x19C: IA32_THERM_STATUS: 88450000
2.) 0x1AA: MSR_MISC_PWR_MGMT: 401CC0 EIST enabled Coordination enabled
OOB Bit 8 reset OOB Bit 18 reset
3.) 0x1B1: IA32_PACKAGE_THERM_STATUS: 88410000
4.) 0x64F: MSR_CORE_PERF_LIMIT_REASONS: 0
A.) 0x1FC: MSR_POWER_CTL: 3C005D : C1E disable : EEO disable : RHO disable
5.) 0x771: IA32_HWP_CAPABILITIES (performance): 10B2930 : high 48 :
guaranteed 41 : efficient 11 : lowest 1
6.) 0x774: IA32_HWP_REQUEST: CPU 0-11 :
raw: 80003001 : 80003001 : 80003001 : 80003001 : 80003001 :
80003001 : 80003001 : 80003001 : 80003001 : 80003001 : 80003001 :
80003001 :
min: 1 : 1 : 1 : 1 : 1 :
1 : 1 : 1 : 1 : 1 : 1 : 1 :
max: 48 : 48 : 48 : 48 : 48 :
48 : 48 : 48 : 48 : 48 : 48 : 48 :
des: 0 : 0 : 0 : 0 : 0 :
0 : 0 : 0 : 0 : 0 : 0 : 0 :
epp: 128 : 128 : 128 : 128 : 128 :
128 : 128 : 128 : 128 : 128 : 128 : 128
:
act: 0 : 0 : 0 : 0 : 0 :
0 : 0 : 0 : 0 : 0 : 0 : 0 :
7.) 0x777: IA32_HWP_STATUS: 0 : high 0 : guaranteed 0 : efficient 0 : lowest 0
...
... Doug