# \[PATCH v2 06/17\] clk: spacemit: k3: parent eDP/DP pixel clock to the PHY PLL - From: Cody Kang via B4 Relay \ - Date: 2026-08-09 13:15:43 - List: linux-phy - Page: https://ratatoskr.run/linux-phy/2026/08/17388303 - Thread: https://ratatoskr.run/dri-devel/2026/08/17388290/t.md ```text From: Cody Kang The APMU eDP/DP pixel-clock muxes were parented to a placeholder, because their real parents (the DP PHY PLLs) did not exist as clocks yet. They do now, so point each mux at its PLL and let the pixel clock reach the controller through the clock framework. Signed-off-by: Cody Kang --- v2: - no change --- drivers/clk/spacemit/ccu-k3.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/spacemit/ccu-k3.c b/drivers/clk/spacemit/ccu-k3.c index cb0c4277f72a8..afbbbd797826d 100644 --- a/drivers/clk/spacemit/ccu-k3.c +++ b/drivers/clk/spacemit/ccu-k3.c @@ -937,13 +937,13 @@ CCU_MUX_DIV_GATE_FC_DEFINE(ufs_aclk, ufs_aclk_parents, APMU_UFS_CLK_RES_CTRL, 5, static const struct clk_parent_data edp0_pclk_parents[] = { CCU_PARENT_HW(lcd_pxclk), - CCU_PARENT_NAME(external_clk), + CCU_PARENT_NAME(edp0_pll_pxclk), }; CCU_MUX_GATE_DEFINE(edp0_pxclk, edp0_pclk_parents, APMU_LCD_EDP_CTRL, 2, 1, BIT(1), 0); static const struct clk_parent_data edp1_pclk_parents[] = { CCU_PARENT_HW(dsi4ln2_lcd_pxclk), - CCU_PARENT_NAME(external_clk), + CCU_PARENT_NAME(edp1_pll_pxclk), }; CCU_MUX_GATE_DEFINE(edp1_pxclk, edp1_pclk_parents, APMU_LCD_EDP_CTRL, 18, 1, BIT(17), 0); -- 2.43.0 -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy ```