Re: [PATCH 2/2] net: stmmac: Add Ingenic SoCs MAC support.
From: Andrew Lunn <andrew@lunn.ch>
Date: 2021-06-08 00:02:07
Also in:
linux-arm-kernel, linux-devicetree, lkml, netdev
quoted hunk ↗ jump to hunk
config DWMAC_ROCKCHIP tristate "Rockchip dwmac support" - default ARCH_ROCKCHIP + default MACH_ROCKCHIP depends on OF && (ARCH_ROCKCHIP || COMPILE_TEST) select MFD_SYSCON help@@ -164,7 +176,7 @@ config DWMAC_STI config DWMAC_STM32 tristate "STM32 DWMAC support" - default ARCH_STM32 + default MACH_STM32
It would be good to explain in the commit message why you are changing these two. It is not obvious.
+static int jz4775_mac_set_mode(struct plat_stmmacenet_data *plat_dat)
+{
+ struct ingenic_mac *mac = plat_dat->bsp_priv;
+ int val;
+
+ switch (plat_dat->interface) {
+ case PHY_INTERFACE_MODE_MII:
+ val = FIELD_PREP(MACPHYC_TXCLK_SEL_MASK, MACPHYC_TXCLK_SEL_INPUT) |
+ FIELD_PREP(MACPHYC_PHY_INFT_MASK, MACPHYC_PHY_INFT_MII);
+ pr_debug("MAC PHY Control Register: PHY_INTERFACE_MODE_MII\n");
+ break;
+
+ case PHY_INTERFACE_MODE_GMII:
+ val = FIELD_PREP(MACPHYC_TXCLK_SEL_MASK, MACPHYC_TXCLK_SEL_INPUT) |
+ FIELD_PREP(MACPHYC_PHY_INFT_MASK, MACPHYC_PHY_INFT_GMII);
+ pr_debug("MAC PHY Control Register: PHY_INTERFACE_MODE_GMII\n");
+ break;
+
+ case PHY_INTERFACE_MODE_RMII:
+ val = FIELD_PREP(MACPHYC_TXCLK_SEL_MASK, MACPHYC_TXCLK_SEL_INPUT) |
+ FIELD_PREP(MACPHYC_PHY_INFT_MASK, MACPHYC_PHY_INFT_RMII);
+ pr_debug("MAC PHY Control Register: PHY_INTERFACE_MODE_RMII\n");
+ break;
+
+ case PHY_INTERFACE_MODE_RGMII:What about the other three RGMII modes?
+ case PHY_INTERFACE_MODE_RGMII: + val = FIELD_PREP(MACPHYC_TX_SEL_MASK, MACPHYC_TX_SEL_DELAY) | + FIELD_PREP(MACPHYC_TX_DELAY_MASK, MACPHYC_TX_DELAY_63_UNIT) | + FIELD_PREP(MACPHYC_RX_SEL_MASK, MACPHYC_RX_SEL_ORIGIN) | + FIELD_PREP(MACPHYC_PHY_INFT_MASK, MACPHYC_PHY_INFT_RGMII);
What exactly does MACPHYC_TX_DELAY_63_UNIT mean here? Ideally, the MAC should not be adding any RGMII delays. It should however pass mode through to the PHY, so it can add the delays, if the mode indicates it should, e.g. PHY_INTERFACE_MODE_RGMII_ID. This is also why you should be handling all 4 RGMII modes here, not just one. Andrew