Add support type switch by pericfg register between USB3, PCIe,
SATA, SGMII, this is used to replace the way through efuse or
jumper.
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
.../devicetree/bindings/phy/mediatek,tphy.yaml | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
@@ -201,6 +201,22 @@ patternProperties:Specify the flag to enable BC1.2 if support ittype:boolean+mediatek,syscon-type:+$ref:/schemas/types.yaml#/definitions/phandle-array+maxItems:1+description:+A phandle to syscon used to access the register of type switch,+the field should always be 3 cells long.+items:+items:+-description:+The first cell represents a phandle to syscon+-description:+The second cell represents the register offset+-description:+The third cell represents the index of config segment+enum:[0,1,2,3]+required:-reg-"#phy-cells"
--
2.18.0
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Add support type switch between USB3, PCIe, SATA and SGMII by
pericfg register, this is used to take the place of efuse or
jumper.
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
drivers/phy/mediatek/phy-mtk-tphy.c | 84 ++++++++++++++++++++++++++++-
1 file changed, 82 insertions(+), 2 deletions(-)
@@ -969,6 +982,64 @@ static void u2_phy_props_set(struct mtk_tphy *tphy,}}+/* type switch for usb3/pcie/sgmii/sata */+staticintphy_type_syscon_get(structmtk_phy_instance*instance,+structdevice_node*dn)+{+structof_phandle_argsargs;+intret;++/* type switch function is optional */+if(!of_property_read_bool(dn,"mediatek,syscon-type"))+return0;++ret=of_parse_phandle_with_fixed_args(dn,"mediatek,syscon-type",+2,0,&args);+if(ret)+returnret;++instance->type_sw_reg=args.args[0];+instance->type_sw_index=args.args[1]&0x3;/* <=3 */+instance->type_sw=syscon_node_to_regmap(args.np);+of_node_put(args.np);+dev_info(&instance->phy->dev,"type_sw - reg %#x, index %d\n",+instance->type_sw_reg,instance->type_sw_index);++returnPTR_ERR_OR_ZERO(instance->type_sw);+}++staticintphy_type_set(structmtk_phy_instance*instance)+{+inttype;+u32mask;++if(!instance->type_sw)+return0;++switch(instance->type){+casePHY_TYPE_USB3:+type=RG_PHY_SW_USB3;+break;+casePHY_TYPE_PCIE:+type=RG_PHY_SW_PCIE;+break;+casePHY_TYPE_SGMII:+type=RG_PHY_SW_SGMII;+break;+casePHY_TYPE_SATA:+type=RG_PHY_SW_SATA;+break;+casePHY_TYPE_USB2:+default:+return0;+}++mask=RG_PHY_SW_TYPE<<(instance->type_sw_index*BITS_PER_BYTE);+regmap_update_bits(instance->type_sw,instance->type_sw_reg,mask,type);++return0;+}+staticintmtk_phy_init(structphy*phy){structmtk_phy_instance*instance=phy_get_drvdata(phy);
@@ -993,6 +1064,9 @@ static int mtk_phy_init(struct phy *phy)casePHY_TYPE_SATA:sata_phy_instance_init(tphy,instance);break;+casePHY_TYPE_SGMII:+/* nothing to do, only used to set type */+break;default:dev_err(tphy->dev,"incompatible PHY type\n");clk_bulk_disable_unprepare(TPHY_CLKS_CNT,instance->clks);
@@ -318,8 +320,7 @@ struct mtk_phy_instance {structu2phy_banksu2_banks;structu3phy_banksu3_banks;};-structclk*ref_clk;/* reference clock of (digital) phy */-structclk*da_ref_clk;/* reference clock of analog phy */+structclk_bulk_dataclks[TPHY_CLKS_CNT];u32index;u8type;inteye_src;
@@ -974,18 +975,9 @@ static int mtk_phy_init(struct phy *phy)structmtk_tphy*tphy=dev_get_drvdata(phy->dev.parent);intret;-ret=clk_prepare_enable(instance->ref_clk);-if(ret){-dev_err(tphy->dev,"failed to enable ref_clk\n");+ret=clk_bulk_prepare_enable(TPHY_CLKS_CNT,instance->clks);+if(ret)returnret;-}--ret=clk_prepare_enable(instance->da_ref_clk);-if(ret){-dev_err(tphy->dev,"failed to enable da_ref\n");-clk_disable_unprepare(instance->ref_clk);-returnret;-}switch(instance->type){casePHY_TYPE_USB2:
@@ -1047,8 +1038,7 @@ static int mtk_phy_exit(struct phy *phy)if(instance->type==PHY_TYPE_USB2)u2_phy_instance_exit(tphy,instance);-clk_disable_unprepare(instance->ref_clk);-clk_disable_unprepare(instance->da_ref_clk);+clk_bulk_disable_unprepare(TPHY_CLKS_CNT,instance->clks);return0;}
@@ -1211,6 +1201,7 @@ static int mtk_tphy_probe(struct platform_device *pdev)port=0;for_each_child_of_node(np,child_np){structmtk_phy_instance*instance;+structclk_bulk_data*clks;structphy*phy;instance=devm_kzalloc(dev,sizeof(*instance),GFP_KERNEL);
@@ -1247,20 +1238,12 @@ static int mtk_tphy_probe(struct platform_device *pdev)phy_set_drvdata(phy,instance);port++;-instance->ref_clk=devm_clk_get_optional(&phy->dev,"ref");-if(IS_ERR(instance->ref_clk)){-dev_err(dev,"failed to get ref_clk(id-%d)\n",port);-retval=PTR_ERR(instance->ref_clk);+clks=instance->clks;+clks[0].id="ref";/* digital (& analog) clock */+clks[1].id="da_ref";/* analog clock */+retval=devm_clk_bulk_get_optional(&phy->dev,TPHY_CLKS_CNT,clks);+if(retval)gotoput_child;-}--instance->da_ref_clk=-devm_clk_get_optional(&phy->dev,"da_ref");-if(IS_ERR(instance->da_ref_clk)){-dev_err(dev,"failed to get da_ref_clk(id-%d)\n",port);-retval=PTR_ERR(instance->da_ref_clk);-gotoput_child;-}}provider=devm_of_phy_provider_register(dev,mtk_phy_xlate);
--
2.18.0
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@@ -74,20 +75,11 @@ static struct ufs_mtk_phy *get_ufs_mtk_phy(struct phy *generic_phy)staticintufs_mtk_phy_clk_init(structufs_mtk_phy*phy){structdevice*dev=phy->dev;+structclk_bulk_data*clks=phy->clks;-phy->unipro_clk=devm_clk_get(dev,"unipro");-if(IS_ERR(phy->unipro_clk)){-dev_err(dev,"failed to get clock: unipro");-returnPTR_ERR(phy->unipro_clk);-}--phy->mp_clk=devm_clk_get(dev,"mp");-if(IS_ERR(phy->mp_clk)){-dev_err(dev,"failed to get clock: mp");-returnPTR_ERR(phy->mp_clk);-}--return0;+clks[0].id="unipro";+clks[1].id="mp";+returndevm_clk_bulk_get(dev,UFSPHY_CLKS_CNT,clks);}staticvoidufs_mtk_phy_set_active(structufs_mtk_phy*phy)
@@ -1278,6 +1278,7 @@ static int mtk_tphy_probe(struct platform_device *pdev)for_each_child_of_node(np,child_np){structmtk_phy_instance*instance;structclk_bulk_data*clks;+structdevice*subdev;structphy*phy;instance=devm_kzalloc(dev,sizeof(*instance),GFP_KERNEL);
@@ -1295,16 +1296,17 @@ static int mtk_tphy_probe(struct platform_device *pdev)gotoput_child;}+subdev=&phy->dev;retval=of_address_to_resource(child_np,0,&res);if(retval){-dev_err(dev,"failed to get address resource(id-%d)\n",+dev_err(subdev,"failed to get address resource(id-%d)\n",port);gotoput_child;}-instance->port_base=devm_ioremap_resource(&phy->dev,&res);+instance->port_base=devm_ioremap_resource(subdev,&res);if(IS_ERR(instance->port_base)){-dev_err(dev,"failed to remap phy regs\n");+dev_err(subdev,"failed to remap phy regs\n");retval=PTR_ERR(instance->port_base);gotoput_child;}
@@ -1317,7 +1319,7 @@ static int mtk_tphy_probe(struct platform_device *pdev)clks=instance->clks;clks[0].id="ref";/* digital (& analog) clock */clks[1].id="da_ref";/* analog clock */-retval=devm_clk_bulk_get_optional(&phy->dev,TPHY_CLKS_CNT,clks);+retval=devm_clk_bulk_get_optional(subdev,TPHY_CLKS_CNT,clks);if(retval)gotoput_child;
--
2.18.0
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From: Rob Herring <robh@kernel.org> Date: 2021-08-02 21:33:46
On Wed, 28 Jul 2021 15:58:23 +0800, Chunfeng Yun wrote:
Add support type switch by pericfg register between USB3, PCIe,
SATA, SGMII, this is used to replace the way through efuse or
jumper.
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
.../devicetree/bindings/phy/mediatek,tphy.yaml | 16 ++++++++++++++++
1 file changed, 16 insertions(+)