diff v10→v5 (patch 1) | series

Inter-revision diff: patch 1

Comparing v10 (message) to v5 (message)
--- v10
+++ v5
@@ -1,23 +1,26 @@
-Since commit 691392448065 ("PCI: Cache PCIe Device Capabilities register")
-has already added a new member called devcap in struct pci_dev for
-caching the PCIe Device Capabilities register to avoid reading
-PCI_EXP_DEVCAP multiple times. Use devcap in more needed places.
+It will make sense to store the pcie_devcap value in the pci_dev
+structure instead of reading Device Capabilities Register multiple
+times. The fisrt place to use pcie_devcap is in set_pcie_port_type(),
+get the pcie_devcap value here, then use cached pcie_devcap in the
+needed place.
 
 Acked-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
 Signed-off-by: Dongdong Liu <liudongdong3@huawei.com>
 Reviewed-by: Christoph Hellwig <hch@lst.de>
 ---
- drivers/media/pci/cobalt/cobalt-driver.c |  4 ++--
+ drivers/media/pci/cobalt/cobalt-driver.c |  5 +++--
+ drivers/pci/pci.c                        |  5 +----
  drivers/pci/pcie/aspm.c                  | 11 ++++-------
- drivers/pci/probe.c                      |  7 +------
+ drivers/pci/probe.c                      | 11 +++--------
  drivers/pci/quirks.c                     |  3 +--
- 4 files changed, 8 insertions(+), 17 deletions(-)
+ include/linux/pci.h                      |  1 +
+ 6 files changed, 13 insertions(+), 23 deletions(-)
 
 diff --git a/drivers/media/pci/cobalt/cobalt-driver.c b/drivers/media/pci/cobalt/cobalt-driver.c
-index 16af58f2f93c..bc04184f1f74 100644
+index 839503e..7ec50d7 100644
 --- a/drivers/media/pci/cobalt/cobalt-driver.c
 +++ b/drivers/media/pci/cobalt/cobalt-driver.c
-@@ -193,11 +193,11 @@ void cobalt_pcie_status_show(struct cobalt *cobalt)
+@@ -193,11 +193,12 @@ void cobalt_pcie_status_show(struct cobalt *cobalt)
  		return;
  
  	/* Device */
@@ -26,13 +29,33 @@
  	pcie_capability_read_word(pci_dev, PCI_EXP_DEVSTA, &stat);
  	cobalt_info("PCIe device capability 0x%08x: Max payload %d\n",
 -		    capa, get_payload_size(capa & PCI_EXP_DEVCAP_PAYLOAD));
-+		    pci_dev->devcap,
-+		    get_payload_size(pci_dev->devcap & PCI_EXP_DEVCAP_PAYLOAD));
++		    pci_dev->pcie_devcap,
++		    get_payload_size(pci_dev->pcie_devcap &
++				     PCI_EXP_DEVCAP_PAYLOAD));
  	cobalt_info("PCIe device control 0x%04x: Max payload %d. Max read request %d\n",
  		    ctrl,
  		    get_payload_size((ctrl & PCI_EXP_DEVCTL_PAYLOAD) >> 5),
+diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
+index b717680..68ccd77 100644
+--- a/drivers/pci/pci.c
++++ b/drivers/pci/pci.c
+@@ -4620,13 +4620,10 @@ EXPORT_SYMBOL(pci_wait_for_pending_transaction);
+  */
+ bool pcie_has_flr(struct pci_dev *dev)
+ {
+-	u32 cap;
+-
+ 	if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET)
+ 		return false;
+ 
+-	pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap);
+-	return cap & PCI_EXP_DEVCAP_FLR;
++	return dev->pcie_devcap & PCI_EXP_DEVCAP_FLR;
+ }
+ EXPORT_SYMBOL_GPL(pcie_has_flr);
+ 
 diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c
-index 013a47f587ce..82d6234a4aa5 100644
+index ac0557a..d637564 100644
 --- a/drivers/pci/pcie/aspm.c
 +++ b/drivers/pci/pcie/aspm.c
 @@ -660,7 +660,7 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist)
@@ -51,11 +74,11 @@
 -		pcie_capability_read_dword(child, PCI_EXP_DEVCAP, &reg32);
  		/* Calculate endpoint L0s acceptable latency */
 -		encoding = (reg32 & PCI_EXP_DEVCAP_L0S) >> 6;
-+		encoding = (child->devcap & PCI_EXP_DEVCAP_L0S) >> 6;
++		encoding = (child->pcie_devcap & PCI_EXP_DEVCAP_L0S) >> 6;
  		acceptable->l0s = calc_l0s_acceptable(encoding);
  		/* Calculate endpoint L1 acceptable latency */
 -		encoding = (reg32 & PCI_EXP_DEVCAP_L1) >> 9;
-+		encoding = (child->devcap & PCI_EXP_DEVCAP_L1) >> 9;
++		encoding = (child->pcie_devcap & PCI_EXP_DEVCAP_L1) >> 9;
  		acceptable->l1 = calc_l1_acceptable(encoding);
  
  		pcie_aspm_check_latency(child);
@@ -73,15 +96,26 @@
  		 */
 -		pcie_capability_read_dword(child, PCI_EXP_DEVCAP, &reg32);
 -		if (!(reg32 & PCI_EXP_DEVCAP_RBER) && !aspm_force) {
-+		if (!(child->devcap & PCI_EXP_DEVCAP_RBER) && !aspm_force) {
++		if (!(child->pcie_devcap & PCI_EXP_DEVCAP_RBER) && !aspm_force) {
  			pci_info(child, "disabling ASPM on pre-1.1 PCIe device.  You can enable it with 'pcie_aspm=force'\n");
  			return -EINVAL;
  		}
 diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
-index d9fc02a71baa..96ecdf34f931 100644
+index 2752046..76ddc89 100644
 --- a/drivers/pci/probe.c
 +++ b/drivers/pci/probe.c
-@@ -2044,18 +2044,13 @@ static void pci_configure_mps(struct pci_dev *dev)
+@@ -1498,8 +1498,8 @@ void set_pcie_port_type(struct pci_dev *pdev)
+ 	pdev->pcie_cap = pos;
+ 	pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, &reg16);
+ 	pdev->pcie_flags_reg = reg16;
+-	pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, &reg16);
+-	pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
++	pci_read_config_dword(pdev, pos + PCI_EXP_DEVCAP, &pdev->pcie_devcap);
++	pdev->pcie_mpss = pdev->pcie_devcap & PCI_EXP_DEVCAP_PAYLOAD;
+ 
+ 	parent = pci_upstream_bridge(pdev);
+ 	if (!parent)
+@@ -2009,18 +2009,13 @@ static void pci_configure_mps(struct pci_dev *dev)
  int pci_configure_extended_tags(struct pci_dev *dev, void *ign)
  {
  	struct pci_host_bridge *host;
@@ -97,24 +131,36 @@
 -		return 0;
 -
 -	if (!(cap & PCI_EXP_DEVCAP_EXT_TAG))
-+	if (!(dev->devcap & PCI_EXP_DEVCAP_EXT_TAG))
++	if (!(dev->pcie_devcap & PCI_EXP_DEVCAP_EXT_TAG))
  		return 0;
  
  	ret = pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
 diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
-index 4537d1ea14fd..1bd0d610f3e0 100644
+index dcb229d..b89b438 100644
 --- a/drivers/pci/quirks.c
 +++ b/drivers/pci/quirks.c
-@@ -5260,8 +5260,7 @@ static void quirk_intel_qat_vf_cap(struct pci_dev *pdev)
+@@ -5073,8 +5073,7 @@ static void quirk_intel_qat_vf_cap(struct pci_dev *pdev)
  		pdev->pcie_cap = pos;
  		pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, &reg16);
  		pdev->pcie_flags_reg = reg16;
 -		pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, &reg16);
 -		pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
-+		pdev->pcie_mpss = pdev->devcap & PCI_EXP_DEVCAP_PAYLOAD;
++		pdev->pcie_mpss = pdev->pcie_devcap & PCI_EXP_DEVCAP_PAYLOAD;
  
  		pdev->cfg_size = PCI_CFG_SPACE_EXP_SIZE;
  		if (pci_read_config_dword(pdev, PCI_CFG_SPACE_SIZE, &status) !=
+diff --git a/include/linux/pci.h b/include/linux/pci.h
+index 2430650..0674161 100644
+--- a/include/linux/pci.h
++++ b/include/linux/pci.h
+@@ -340,6 +340,7 @@ struct pci_dev {
+ 	u8		rom_base_reg;	/* Config register controlling ROM */
+ 	u8		pin;		/* Interrupt pin this device uses */
+ 	u16		pcie_flags_reg;	/* Cached PCIe Capabilities Register */
++	u32		pcie_devcap;	/* Cached Device Capabilities Register */
+ 	unsigned long	*dma_alias_mask;/* Mask of enabled devfn aliases */
+ 
+ 	struct pci_driver *driver;	/* Driver bound to this device */
 -- 
-2.22.0
+2.7.4
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