# RE: \[PATCH V3 05/13\] HV: Add Write/Read MSR registers via ghcb page

- From: Michael Kelley \<hidden\>
- Date: 2021-08-13 20:26:32 
- List: linux-hyperv
- Page: https://ratatoskr.run/linux-hyperv/2021/08/1477486
- Thread: https://ratatoskr.run/xen-devel/2021/08/1472230/t.md

```text
From: Michael Kelley <redacted> Sent: Friday, August 13, 2021 12:31 PM
> To: Tianyu Lan <redacted>; KY Srinivasan <redacted>; Haiyang Zhang <haiyangz@microsoft.com>;
> Stephen Hemminger [ref]; wei.liu@kernel.org; Dexuan Cui [ref];
> tglx@linutronix.de; mingo@redhat.com; bp@alien8.de; x86@kernel.org; hpa@zytor.com; dave.hansen@linux.intel.com;
> luto@kernel.org; peterz@infradead.org; konrad.wilk@oracle.com; boris.ostrovsky@oracle.com; jgross@suse.com;
> sstabellini@kernel.org; joro@8bytes.org; will@kernel.org; davem@davemloft.net; kuba@kernel.org; jejb@linux.ibm.com;
> martin.petersen@oracle.com; arnd@arndb.de; hch@lst.de; m.szyprowski@samsung.com; robin.murphy@arm.com;
> thomas.lendacky@amd.com; brijesh.singh@amd.com; ardb@kernel.org; Tianyu Lan [ref];
> pgonda@google.com; martin.b.radev@gmail.com; akpm@linux-foundation.org; kirill.shutemov@linux.intel.com;
> rppt@kernel.org; sfr@canb.auug.org.au; saravanand@fb.com; krish.sadhukhan@oracle.com;
> aneesh.kumar@linux.ibm.com; xen-devel@lists.xenproject.org; rientjes@google.com; hannes@cmpxchg.org;
> tj@kernel.org
> Cc: <redacted>; <redacted>; <redacted>; linux-
> kernel@vger.kernel.org; linux-scsi@vger.kernel.org; netdev@vger.kernel.org; vkuznets [ref];
> parri.andrea@gmail.com; dave.hansen@intel.com
> Subject: RE: [PATCH V3 05/13] HV: Add Write/Read MSR registers via ghcb page
> 
> From: Tianyu Lan <redacted> Sent: Monday, August 9, 2021 10:56 AM
> > Subject: [PATCH V3 05/13] HV: Add Write/Read MSR registers via ghcb page
> 
> See previous comments about tag in the Subject line.
> 
> > Hyper-V provides GHCB protocol to write Synthetic Interrupt
> > Controller MSR registers in Isolation VM with AMD SEV SNP
> > and these registers are emulated by hypervisor directly.
> > Hyper-V requires to write SINTx MSR registers twice. First
> > writes MSR via GHCB page to communicate with hypervisor
> > and then writes wrmsr instruction to talk with paravisor
> > which runs in VMPL0. Guest OS ID MSR also needs to be set
> > via GHCB.
> >
> > Signed-off-by: Tianyu Lan <redacted>
> > ---
> > Change since v1:
> >          * Introduce sev_es_ghcb_hv_call_simple() and share code
> >            between SEV and Hyper-V code.
> > ---
> >  arch/x86/hyperv/hv_init.c       |  33 ++-------
> >  arch/x86/hyperv/ivm.c           | 110 +++++++++++++++++++++++++++++
> >  arch/x86/include/asm/mshyperv.h |  78 +++++++++++++++++++-
> >  arch/x86/include/asm/sev.h      |   3 +
> >  arch/x86/kernel/cpu/mshyperv.c  |   3 +
> >  arch/x86/kernel/sev-shared.c    |  63 ++++++++++-------
> >  drivers/hv/hv.c                 | 121 ++++++++++++++++++++++----------
> >  include/asm-generic/mshyperv.h  |  12 +++-
> >  8 files changed, 329 insertions(+), 94 deletions(-)
> >
> > diff --git a/arch/x86/hyperv/hv_init.c b/arch/x86/hyperv/hv_init.c
> > index b3683083208a..ab0b33f621e7 100644
> > --- a/arch/x86/hyperv/hv_init.c
> > +++ b/arch/x86/hyperv/hv_init.c
> > @@ -423,7 +423,7 @@ void __init hyperv_init(void)
> >  		goto clean_guest_os_id;
> >
> >  	if (hv_isolation_type_snp()) {
> > -		ms_hyperv.ghcb_base = alloc_percpu(void *);
> > +		ms_hyperv.ghcb_base = alloc_percpu(union hv_ghcb __percpu *);
> 
> union hv_ghcb isn't defined.  It is not added until patch 6 of the series.
> 

Ignore this comment.  My mistake.

Michael
```