# Re: \[PATCH v2 14/19\] video/vga: Add VGA\_IS0\_R

- From: Ville Syrjälä \<hidden\>
- Date: 2025-12-18 16:58:03 
- List: linux-fbdev
- Page: https://ratatoskr.run/linux-fbdev/2025/12/9269013
- Thread: https://ratatoskr.run/intel-gfx/2025/12/12965768/t.md

```text
On Tue, Dec 09, 2025 at 12:55:49PM +0200, Jani Nikula wrote:
> On Tue, 09 Dec 2025, Ville Syrjala [ref] wrote:
> > From: Ville Syrjälä <redacted>
> >
> > Add a proper name for the "Input status register 0" IO address.
> > Currently we have some code that does read addressed using the
> > aliasing VGA_MSR_W define, making it unclear what register we're
> > actually reading.
> >
> > v2: Remove stray '?'
> >
> > Cc: Helge Deller <deller@gmx.de>

Helge, can you toss me an ack to merge this via drm-intel please?

> > Cc: <redacted>
> > Cc: <redacted>
> > Signed-off-by: Ville Syrjälä <redacted>
> 
> Reviewed-by: Jani Nikula <redacted>
> 
> > ---
> >  include/video/vga.h | 1 +
> >  1 file changed, 1 insertion(+)
> >
> > diff --git a/include/video/vga.h b/include/video/vga.h
> > index 468764d6727a..2f13c371800b 100644
> > --- a/include/video/vga.h
> > +++ b/include/video/vga.h
> > @@ -46,6 +46,7 @@
> >  #define VGA_MIS_R   	0x3CC	/* Misc Output Read Register */
> >  #define VGA_MIS_W   	0x3C2	/* Misc Output Write Register */
> >  #define VGA_FTC_R	0x3CA	/* Feature Control Read Register */
> > +#define VGA_IS0_R	0x3C2	/* Input Status Register 0 */
> >  #define VGA_IS1_RC  	0x3DA	/* Input Status Register 1 - color emulation */
> >  #define VGA_IS1_RM  	0x3BA	/* Input Status Register 1 - mono emulation */
> >  #define VGA_PEL_D   	0x3C9	/* PEL Data Register */
> 
> -- 
> Jani Nikula, Intel

-- 
Ville Syrjälä
Intel
```