On Sun Ultra 5, it happens that the dot clock is not set up properly for
some videomodes. For example, if we set the videomode "r1024x768x60" in
the firmware, Linux would incorrectly set a videomode with refresh rate
180Hz when booting (suprisingly, my LCD monitor can display it, although
display quality is very low).
The reason is this: Older mach64 cards set the divider in the register
VCLK_POST_DIV. The register has four 2-bit fields (the field that is
actually used is specified in the lowest two bits of the register
CLOCK_CNTL). The 2 bits select divider "1, 2, 4, 8". On newer mach64 cards,
there's another bit added - the top four bits of PLL_EXT_CNTL extend the
divider selection, so we have possible dividers "1, 2, 4, 8, 3, 5, 6, 12".
The Linux driver clears the top four bits of PLL_EXT_CNTL and never sets
them, so it can work regardless if the card supports them. However, the
sparc64 firmware may set these extended dividers during boot - and the
mach64 driver detects incorrect dot clock in this case.
This patch makes the driver read the additional divider bit from
PLL_EXT_CNTL and calculate the initial refresh rate properly.
Signed-off-by: Mikulas Patocka <mpatocka@redhat.com>
Cc: stable@vger.kernel.org
---
drivers/video/fbdev/aty/atyfb.h | 3 ++-
drivers/video/fbdev/aty/atyfb_base.c | 7 ++++---
drivers/video/fbdev/aty/mach64_ct.c | 10 +++++-----
3 files changed, 11 insertions(+), 9 deletions(-)
Index: linux-stable/drivers/video/fbdev/aty/atyfb.h
=================================--- linux-stable.orig/drivers/video/fbdev/aty/atyfb.h 2018-08-13 21:12:11.000000000 +0200
On Sun Ultra 5, it happens that the dot clock is not set up properly for
some videomodes. For example, if we set the videomode "r1024x768x60" in
the firmware, Linux would incorrectly set a videomode with refresh rate
180Hz when booting (suprisingly, my LCD monitor can display it, although
display quality is very low).
The reason is this: Older mach64 cards set the divider in the register
VCLK_POST_DIV. The register has four 2-bit fields (the field that is
actually used is specified in the lowest two bits of the register
CLOCK_CNTL). The 2 bits select divider "1, 2, 4, 8". On newer mach64 cards,
there's another bit added - the top four bits of PLL_EXT_CNTL extend the
divider selection, so we have possible dividers "1, 2, 4, 8, 3, 5, 6, 12".
The Linux driver clears the top four bits of PLL_EXT_CNTL and never sets
them, so it can work regardless if the card supports them. However, the
sparc64 firmware may set these extended dividers during boot - and the
mach64 driver detects incorrect dot clock in this case.
This patch makes the driver read the additional divider bit from
PLL_EXT_CNTL and calculate the initial refresh rate properly.
Signed-off-by: Mikulas Patocka <mpatocka@redhat.com>
Cc: stable@vger.kernel.org
From: Ville Syrjälä <syrjala@sci.fi> Date: 2018-08-19 10:37:09
On Fri, Aug 17, 2018 at 03:19:37PM -0400, Mikulas Patocka wrote:
quoted hunk
On Sun Ultra 5, it happens that the dot clock is not set up properly for
some videomodes. For example, if we set the videomode "r1024x768x60" in
the firmware, Linux would incorrectly set a videomode with refresh rate
180Hz when booting (suprisingly, my LCD monitor can display it, although
display quality is very low).
The reason is this: Older mach64 cards set the divider in the register
VCLK_POST_DIV. The register has four 2-bit fields (the field that is
actually used is specified in the lowest two bits of the register
CLOCK_CNTL). The 2 bits select divider "1, 2, 4, 8". On newer mach64 cards,
there's another bit added - the top four bits of PLL_EXT_CNTL extend the
divider selection, so we have possible dividers "1, 2, 4, 8, 3, 5, 6, 12".
The Linux driver clears the top four bits of PLL_EXT_CNTL and never sets
them, so it can work regardless if the card supports them. However, the
sparc64 firmware may set these extended dividers during boot - and the
mach64 driver detects incorrect dot clock in this case.
This patch makes the driver read the additional divider bit from
PLL_EXT_CNTL and calculate the initial refresh rate properly.
Signed-off-by: Mikulas Patocka <mpatocka@redhat.com>
Cc: stable@vger.kernel.org
---
drivers/video/fbdev/aty/atyfb.h | 3 ++-
drivers/video/fbdev/aty/atyfb_base.c | 7 ++++---
drivers/video/fbdev/aty/mach64_ct.c | 10 +++++-----
3 files changed, 11 insertions(+), 9 deletions(-)
Index: linux-stable/drivers/video/fbdev/aty/atyfb.h
=================================> --- linux-stable.orig/drivers/video/fbdev/aty/atyfb.h 2018-08-13 21:12:11.000000000 +0200
Not sure about the '5'. That setting is marked as reserved in my docs.
So I guess it doesn't really matter what number we put there.
Reviewed-by: Ville Syrjälä <syrjala@sci.fi>
On Fri, Aug 17, 2018 at 03:19:37PM -0400, Mikulas Patocka wrote:
quoted
On Sun Ultra 5, it happens that the dot clock is not set up properly for
some videomodes. For example, if we set the videomode "r1024x768x60" in
the firmware, Linux would incorrectly set a videomode with refresh rate
180Hz when booting (suprisingly, my LCD monitor can display it, although
display quality is very low).
The reason is this: Older mach64 cards set the divider in the register
VCLK_POST_DIV. The register has four 2-bit fields (the field that is
actually used is specified in the lowest two bits of the register
CLOCK_CNTL). The 2 bits select divider "1, 2, 4, 8". On newer mach64 cards,
there's another bit added - the top four bits of PLL_EXT_CNTL extend the
divider selection, so we have possible dividers "1, 2, 4, 8, 3, 5, 6, 12".
The Linux driver clears the top four bits of PLL_EXT_CNTL and never sets
them, so it can work regardless if the card supports them. However, the
sparc64 firmware may set these extended dividers during boot - and the
mach64 driver detects incorrect dot clock in this case.
This patch makes the driver read the additional divider bit from
PLL_EXT_CNTL and calculate the initial refresh rate properly.
Signed-off-by: Mikulas Patocka <mpatocka@redhat.com>
Cc: stable@vger.kernel.org
---
drivers/video/fbdev/aty/atyfb.h | 3 ++-
drivers/video/fbdev/aty/atyfb_base.c | 7 ++++---
drivers/video/fbdev/aty/mach64_ct.c | 10 +++++-----
3 files changed, 11 insertions(+), 9 deletions(-)
Index: linux-stable/drivers/video/fbdev/aty/atyfb.h
===================================================================
Not sure about the '5'. That setting is marked as reserved in my docs.
So I guess it doesn't really matter what number we put there.
I downloaded documentation here:
http://ftp.nluug.nl/ftp/pub/NetBSD/misc/cegger/hw_manuals/ati/mach64_and_ragepro/
The RAGE XL/XC Register Reference Guide - at page 4-77 it says "select
alternate post dividers", but doesn't say what they are.
At page 4-89 it lists post dividers 1,2,4,8,3,5,6,12. It's hard to say if
they also apply to the PLL_EXT_CNTL register or not.
At lest the divider 3 is valid because the Sparc firmware sets it and it
works as expected.
Mikulas
From: Ville Syrjälä <syrjala@sci.fi> Date: 2018-08-24 11:59:07
On Thu, Aug 23, 2018 at 05:17:20PM -0400, Mikulas Patocka wrote:
On Sun, 19 Aug 2018, Ville Syrjälä wrote:
quoted
On Fri, Aug 17, 2018 at 03:19:37PM -0400, Mikulas Patocka wrote:
quoted
On Sun Ultra 5, it happens that the dot clock is not set up properly for
some videomodes. For example, if we set the videomode "r1024x768x60" in
the firmware, Linux would incorrectly set a videomode with refresh rate
180Hz when booting (suprisingly, my LCD monitor can display it, although
display quality is very low).
The reason is this: Older mach64 cards set the divider in the register
VCLK_POST_DIV. The register has four 2-bit fields (the field that is
actually used is specified in the lowest two bits of the register
CLOCK_CNTL). The 2 bits select divider "1, 2, 4, 8". On newer mach64 cards,
there's another bit added - the top four bits of PLL_EXT_CNTL extend the
divider selection, so we have possible dividers "1, 2, 4, 8, 3, 5, 6, 12".
The Linux driver clears the top four bits of PLL_EXT_CNTL and never sets
them, so it can work regardless if the card supports them. However, the
sparc64 firmware may set these extended dividers during boot - and the
mach64 driver detects incorrect dot clock in this case.
This patch makes the driver read the additional divider bit from
PLL_EXT_CNTL and calculate the initial refresh rate properly.
Signed-off-by: Mikulas Patocka <mpatocka@redhat.com>
Cc: stable@vger.kernel.org
---
drivers/video/fbdev/aty/atyfb.h | 3 ++-
drivers/video/fbdev/aty/atyfb_base.c | 7 ++++---
drivers/video/fbdev/aty/mach64_ct.c | 10 +++++-----
3 files changed, 11 insertions(+), 9 deletions(-)
Index: linux-stable/drivers/video/fbdev/aty/atyfb.h
=================================> > > --- linux-stable.orig/drivers/video/fbdev/aty/atyfb.h 2018-08-13 21:12:11.000000000 +0200
Not sure about the '5'. That setting is marked as reserved in my docs.
So I guess it doesn't really matter what number we put there.
I downloaded documentation here:
http://ftp.nluug.nl/ftp/pub/NetBSD/misc/cegger/hw_manuals/ati/mach64_and_ragepro/
The RAGE XL/XC Register Reference Guide - at page 4-77 it says "select
alternate post dividers", but doesn't say what they are.
At page 4-89 it lists post dividers 1,2,4,8,3,5,6,12. It's hard to say if
they also apply to the PLL_EXT_CNTL register or not.
Oh, I missed the V2CLK reg. Indeed I see the /5 there in my docs as
well.
For the other clocks the Rage II docs I have have the following table:
ALT_VCLKx_POST VCLKx_POST Post Divider
0 00 /1
0 01 /2
0 10 /4
0 11 /8
1 00 /3
1 01 reserved
1 10 /6
1 11 /12
Curiously that table is nowhere to be found in the docs for any of the
more recent chips.
But yeah, given the V2CLK thing /5 seems like a perfectly good
value to use here.
--
Ville Syrjälä
syrjala@sci.fi
http://www.sci.fi/~syrjala/
On Fri, Aug 17, 2018 at 03:19:37PM -0400, Mikulas Patocka wrote:
quoted
On Sun Ultra 5, it happens that the dot clock is not set up properly for
some videomodes. For example, if we set the videomode "r1024x768x60" in
the firmware, Linux would incorrectly set a videomode with refresh rate
180Hz when booting (suprisingly, my LCD monitor can display it, although
display quality is very low).
The reason is this: Older mach64 cards set the divider in the register
VCLK_POST_DIV. The register has four 2-bit fields (the field that is
actually used is specified in the lowest two bits of the register
CLOCK_CNTL). The 2 bits select divider "1, 2, 4, 8". On newer mach64 cards,
there's another bit added - the top four bits of PLL_EXT_CNTL extend the
divider selection, so we have possible dividers "1, 2, 4, 8, 3, 5, 6, 12".
The Linux driver clears the top four bits of PLL_EXT_CNTL and never sets
them, so it can work regardless if the card supports them. However, the
sparc64 firmware may set these extended dividers during boot - and the
mach64 driver detects incorrect dot clock in this case.
This patch makes the driver read the additional divider bit from
PLL_EXT_CNTL and calculate the initial refresh rate properly.
Signed-off-by: Mikulas Patocka <mpatocka@redhat.com>
Cc: stable@vger.kernel.org
---
drivers/video/fbdev/aty/atyfb.h | 3 ++-
drivers/video/fbdev/aty/atyfb_base.c | 7 ++++---
drivers/video/fbdev/aty/mach64_ct.c | 10 +++++-----
3 files changed, 11 insertions(+), 9 deletions(-)
Index: linux-stable/drivers/video/fbdev/aty/atyfb.h
=================================>> --- linux-stable.orig/drivers/video/fbdev/aty/atyfb.h 2018-08-13 21:12:11.000000000 +0200
Not sure about the '5'. That setting is marked as reserved in my docs.
So I guess it doesn't really matter what number we put there.
Reviewed-by: Ville Syrj채l채 <syrjala@sci.fi>
Patch queued for 4.20, thanks.
Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung R&D Institute Poland
Samsung Electronics