Re: [Xen-devel] [PATCH v7 5/9] PCI: Add pci_iomap_wc() variants

On Fri, 2015-06-26 at 15:41 -0700, Luis R. Rodriguez wrote:

quoted

It wasn't nullified for the main user at the time, the fb. And I
mentioned an IB adapter or two for which the code had been hand

tuned.

This still means there could be some affected drivers when used on
powerpc, no?

Yes. In fact what about things like ARM who also have barriers in their
writel() ? Won't they also break WC ?

I'm trying to work with the architect and designers here to figure out
exactly where we stand and what we can do. As spelled out by our
architecture, things don't look great, because basically, we only have
attribute bit (garded) which when not set implies both WC and out of
order (& prefetch), and unclear barrier semantics in that case as well.

I *think* we might be able to settle with something along the lines of
"writel_relaxed() will allow combine on a WC mapping" but how I'm going
to get there is TBD.

It would be interesting to clarify the semantics of using the relaxed
accessors in combination with WC anyway. I wouldn't mind if the
definition involved also relaxing general ordering :-) It would
definitely make my life easier.

Cheers,
Ben.

On Fri, Jun 26, 2015 at 4:54 PM, Benjamin Herrenschmidt
[off-list ref] wrote:

On Fri, 2015-06-26 at 15:41 -0700, Luis R. Rodriguez wrote:

quoted

quoted

It wasn't nullified for the main user at the time, the fb. And I
mentioned an IB adapter or two for which the code had been hand

tuned.

This still means there could be some affected drivers when used on
powerpc, no?

Yes. In fact what about things like ARM who also have barriers in their
writel() ? Won't they also break WC ?

Not sure if they have that write-combine notion on their CPUs /
interconnects. Russel, Stefano, does ARM have write-combining ?

 Luis