[RFC 03/23] OMAPDSS: raw read and write endian fix

@@ -228,12 +228,12 @@ static unsigned long dispc_plane_lclk_rate(enum omap_plane plane);
 
 static inline void dispc_write_reg(const u16 idx, u32 val)
 {
-	__raw_writel(val, dispc.base + idx);
+	writel_relaxed(val, dispc.base + idx);
 }
 
 static inline u32 dispc_read_reg(const u16 idx)
 {
-	return __raw_readl(dispc.base + idx);
+	return readl_relaxed(dispc.base + idx);
 }
 
 static u32 mgr_fld_read(enum omap_channel channel, enum mgr_reg_fields regfld)

@@ -414,7 +414,7 @@ static inline void dsi_write_reg(struct platform_device *dsidev,
 {
 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 
-	__raw_writel(val, dsi->base + idx.idx);
+	writel_relaxed(val, dsi->base + idx.idx);
 }
 
 static inline u32 dsi_read_reg(struct platform_device *dsidev,

@@ -422,7 +422,7 @@ static inline u32 dsi_read_reg(struct platform_device *dsidev,
 {
 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 
-	return __raw_readl(dsi->base + idx.idx);
+	return readl_relaxed(dsi->base + idx.idx);
 }
 
 static void dsi_bus_lock(struct omap_dss_device *dssdev)

@@ -104,12 +104,12 @@ static const char * const dss_generic_clk_source_names[] = {
 
 static inline void dss_write_reg(const struct dss_reg idx, u32 val)
 {
-	__raw_writel(val, dss.base + idx.idx);
+	writel_relaxed(val, dss.base + idx.idx);
 }
 
 static inline u32 dss_read_reg(const struct dss_reg idx)
 {
-	return __raw_readl(dss.base + idx.idx);
+	return readl_relaxed(dss.base + idx.idx);
 }
 
 #define SR(reg) \

@@ -122,12 +122,12 @@ static struct {
 
 static inline void rfbi_write_reg(const struct rfbi_reg idx, u32 val)
 {
-	__raw_writel(val, rfbi.base + idx.idx);
+	writel_relaxed(val, rfbi.base + idx.idx);
 }
 
 static inline u32 rfbi_read_reg(const struct rfbi_reg idx)
 {
-	return __raw_readl(rfbi.base + idx.idx);
+	return readl_relaxed(rfbi.base + idx.idx);
 }
 
 static int rfbi_runtime_get(void)

@@ -263,8 +263,8 @@ static void rfbi_write_pixels(const void __iomem *buf, int scr_width,
 		for (; h; --h) {
 			for (i = 0; i < w; ++i) {
 				const u8 __iomem *b = (const u8 __iomem *)pd;
-				rfbi_write_reg(RFBI_PARAM, __raw_readb(b+1));
-				rfbi_write_reg(RFBI_PARAM, __raw_readb(b+0));
+				rfbi_write_reg(RFBI_PARAM, readb_relaxed(b+1));
+				rfbi_write_reg(RFBI_PARAM, readb_relaxed(b+0));
 				++pd;
 			}
 			pd += horiz_offset;

@@ -277,9 +277,9 @@ static void rfbi_write_pixels(const void __iomem *buf, int scr_width,
 		for (; h; --h) {
 			for (i = 0; i < w; ++i) {
 				const u8 __iomem *b = (const u8 __iomem *)pd;
-				rfbi_write_reg(RFBI_PARAM, __raw_readb(b+2));
-				rfbi_write_reg(RFBI_PARAM, __raw_readb(b+1));
-				rfbi_write_reg(RFBI_PARAM, __raw_readb(b+0));
+				rfbi_write_reg(RFBI_PARAM, readb_relaxed(b+2));
+				rfbi_write_reg(RFBI_PARAM, readb_relaxed(b+1));
+				rfbi_write_reg(RFBI_PARAM, readb_relaxed(b+0));
 				++pd;
 			}
 			pd += horiz_offset;

@@ -291,7 +291,7 @@ static void rfbi_write_pixels(const void __iomem *buf, int scr_width,
 
 		for (; h; --h) {
 			for (i = 0; i < w; ++i) {
-				rfbi_write_reg(RFBI_PARAM, __raw_readw(pd));
+				rfbi_write_reg(RFBI_PARAM, readw_relaxed(pd));
 				++pd;
 			}
 			pd += horiz_offset;

@@ -43,13 +43,13 @@
 static inline void hdmi_write_reg(void __iomem *base_addr,
 				const u16 idx, u32 val)
 {
-	__raw_writel(val, base_addr + idx);
+	writel_relaxed(val, base_addr + idx);
 }
 
 static inline u32 hdmi_read_reg(void __iomem *base_addr,
 				const u16 idx)
 {
-	return __raw_readl(base_addr + idx);
+	return readl_relaxed(base_addr + idx);
 }
 
 static inline void __iomem *hdmi_wp_base(struct hdmi_ip_data *ip_data)

@@ -309,12 +309,12 @@ static struct {
 
 static inline void venc_write_reg(int idx, u32 val)
 {
-	__raw_writel(val, venc.base + idx);
+	writel_relaxed(val, venc.base + idx);
 }
 
 static inline u32 venc_read_reg(int idx)
 {
-	u32 l = __raw_readl(venc.base + idx);
+	u32 l = readl_relaxed(venc.base + idx);
 	return l;
 }
 

@@ -82,18 +82,18 @@ static void draw_pixel(struct fb_info *fbi, int x, int y, unsigned color)
 		g = g * 64 / 256;
 		b = b * 32 / 256;
 
-		__raw_writew((r << 11) | (g << 5) | (b << 0), p);
+		writew_relaxed((r << 11) | (g << 5) | (b << 0), p);
 	} else if (var->bits_per_pixel = 24) {
 		u8 __iomem *p = (u8 __iomem *)addr;
 		p += (y * line_len + x) * 3;
 
-		__raw_writeb(b, p + 0);
-		__raw_writeb(g, p + 1);
-		__raw_writeb(r, p + 2);
+		writeb_relaxed(b, p + 0);
+		writeb_relaxed(g, p + 1);
+		writeb_relaxed(r, p + 2);
 	} else if (var->bits_per_pixel = 32) {
 		u32 __iomem *p = (u32 __iomem *)addr;
 		p += y * line_len + x;
-		__raw_writel(color, p);
+		writel_relaxed(color, p);
 	}
 }
 

@@ -82,17 +82,17 @@ static bool vrfb_loaded;
 
 static void omap2_sms_write_rot_control(u32 val, unsigned ctx)
 {
-	__raw_writel(val, vrfb_base + SMS_ROT_CONTROL(ctx));
+	writel_relaxed(val, vrfb_base + SMS_ROT_CONTROL(ctx));
 }
 
 static void omap2_sms_write_rot_size(u32 val, unsigned ctx)
 {
-	__raw_writel(val, vrfb_base + SMS_ROT_SIZE(ctx));
+	writel_relaxed(val, vrfb_base + SMS_ROT_SIZE(ctx));
 }
 
 static void omap2_sms_write_rot_physical_ba(u32 val, unsigned ctx)
 {
-	__raw_writel(val, vrfb_base + SMS_ROT_PHYSICAL_BA(ctx));
+	writel_relaxed(val, vrfb_base + SMS_ROT_PHYSICAL_BA(ctx));
 }
 
 static inline void restore_hw_context(int ctx)