PiBIaSwNCj4NCj4gSSBhbSB3b3JraW5nIG9uIERUIGJpbmRpbmcgZm9yIFRlZ3JhIERWRlMuDQo+
DQo+IEZvciBUZWdyYSwgRFZGUyBub2RlIG1haW5seSBjb25zaXN0cyBvZiBmcmVxdWVuY3kgYW5k
IHZvbHRhZ2UgcGFpcnMuIA0KPiBGcmVxdWVuY3kgaW4gdGhlIHBhaXIgbWF5IGNoYW5nZSBmb3Ig
ZGlmZmVyZW50IHByb2Nlc3MuIEUuZy4gZm9yIHByb2Nlc3MgDQo+IDEgQ1BVIGNsb2NrIGZyZXF1
ZW5jeSBjb3VsZCBiZSA5MDBNSHogYXQgMVYgd2hpbGUgZm9yIHByb2Nlc3MgMiBpdCBjb3VsZCAN
Cj4gYmUgMUdIeiBhdCAxVi4NCj4gVGVncmEgdXNlcyB2ZW5kb3Igc3BlY2lmaWMgaWRzIHRvIGlk
ZW50aWZ5IHRoZSBjb3JyZWN0IGZyZXF1ZW5jeSB0YWJsZS4NCg0KSGVsbG8sDQoNCkl0IHNlZW1z
IHRoYXQgaW4gdGhlIGV4YW1wbGUsIHRoZSB2YWx1ZXMgaW4gInZvbHRhZ2UtYXJyYXkiIGFuZA0K
ImZyZXF1ZW5jaWVzIiBhcmUgc3dpdGNoZWQuDQoNCkFueXdheSwgd2hhdCBhYm91dCBTb0NzIHRo
YXQgcmVhZHMgaW5mb3JtYXRpb24gZnJvbSBJRU0gKG9yIGFueSBvdGhlciBtb2R1bGUpDQogdG8g
bWVhc3VyZSBnYXRlIGRlbGF5cyBvciBzb21lIG90aGVyIHZhbHVlIHRvIHNldCB0aGUgYXBwcmlv
cmF0ZSB2b2x0YWdlIHZhbHVlcw0KIGZvciBldmVyeSBwb3NzaWJsZSBmcmVxdWVuY3k/IEkgcmVt
ZW1iZXIgc29tZSBvZiBFeHlub3MgU29DcyBoYXZlIGJlZW4gZG9pbmcNCiBpdDsgZHluYW1pY2Fs
bHkgbWVhc3VyZSB0aGUgY2hhcmFjdGVyaXN0aWNzIGF0IGJvb3QtdXAgdGltZSBhbmQgYXBwbHkg
dm9sdGFnZXMNCiBhY2NvcmRpbmdseTsgdGhleSBjb3VsZG4ndCBpZGVudGlmeSBpdCBiYXNlZCBv
biB0aGUgY2hpcC1pZCBvciBzaW1wbHkgYnkgcmVhZGluZw0KIGEgc2luZ2xlIHJlZ2lzdGVyLg0K
DQoNCkNoZWVycyENCk15dW5nSm9vLg0KDQo+IA0KPiBGb2xsb3dpbmcgaXMgdGhlIHByb3Bvc2Vk
IGJpbmRpbmcgZm9yIHZvbHRhZ2UgYW5kIGZyZXF1ZW5jeSB0YWJsZXMgdXNlZCANCj4gaW4gRFZG
Uy4gTG9va2luZyBmb3IgY29tbWVudHMvc3VnZ2VzdGlvbnMgdG8gbWFrZSBpdCBnZW5lcmljLg0K
DQo
On Wed, Jul 11, 2012 at 03:08:14PM +0200, 함명주 wrote:
quoted
Hi,
I am working on DT binding for Tegra DVFS.
For Tegra, DVFS node mainly consists of frequency and voltage pairs.
Frequency in the pair may change for different process. E.g. for process
1 CPU clock frequency could be 900MHz at 1V while for process 2 it could
be 1GHz at 1V.
Tegra uses vendor specific ids to identify the correct frequency table.
Hello,
It seems that in the example, the values in "voltage-array" and
"frequencies" are switched.
Anyway, what about SoCs that reads information from IEM (or any other module)
to measure gate delays or some other value to set the appriorate voltage values
for every possible frequency? I remember some of Exynos SoCs have been doing
it; dynamically measure the characteristics at boot-up time and apply voltages
accordingly; they couldn't identify it based on the chip-id or simply by reading
a single register.
But in that case you would have a nominal voltage for each OPP which gets
adjusted at boottime or runtime depending on the exact silicon characteristics?
I would say the DT binding should then specify 1 table with the nominal values
and leave the dynamics to the driver.
Cheers,
Peter.
On Wed, Jul 11, 2012 at 03:08:14PM +0200, 함명주 wrote:
quoted
Hi,
I am working on DT binding for Tegra DVFS.
For Tegra, DVFS node mainly consists of frequency and voltage pairs.
Frequency in the pair may change for different process. E.g. for process
1 CPU clock frequency could be 900MHz at 1V while for process 2 it could
be 1GHz at 1V.
Tegra uses vendor specific ids to identify the correct frequency table.
Hello,
It seems that in the example, the values in "voltage-array" and
"frequencies" are switched.
Anyway, what about SoCs that reads information from IEM (or any other module)
to measure gate delays or some other value to set the appriorate voltage values
for every possible frequency? I remember some of Exynos SoCs have been doing
it; dynamically measure the characteristics at boot-up time and apply voltages
accordingly; they couldn't identify it based on the chip-id or simply by reading
a single register.
But in that case you would have a nominal voltage for each OPP which gets
adjusted at boottime or runtime depending on the exact silicon characteristics?
I would say the DT binding should then specify 1 table with the nominal values
and leave the dynamics to the driver.
Cheers,
Peter.
On Wednesday 11 July 2012 07:19 PM, Peter De Schrijver wrote:
On Wed, Jul 11, 2012 at 03:08:14PM +0200, 함명주 wrote:
quoted
quoted
Hi,
I am working on DT binding for Tegra DVFS.
For Tegra, DVFS node mainly consists of frequency and voltage pairs.
Frequency in the pair may change for different process. E.g. for process
1 CPU clock frequency could be 900MHz at 1V while for process 2 it could
be 1GHz at 1V.
Tegra uses vendor specific ids to identify the correct frequency table.
Hello,
It seems that in the example, the values in "voltage-array" and
"frequencies" are switched.
Anyway, what about SoCs that reads information from IEM (or any other module)
to measure gate delays or some other value to set the appriorate voltage values
for every possible frequency? I remember some of Exynos SoCs have been doing
it; dynamically measure the characteristics at boot-up time and apply voltages
accordingly; they couldn't identify it based on the chip-id or simply by reading
a single register.
But in that case you would have a nominal voltage for each OPP which gets
adjusted at boottime or runtime depending on the exact silicon characteristics?
I would say the DT binding should then specify 1 table with the nominal values
and leave the dynamics to the driver.
It makes sense or is it different than this?
Cheers,
Peter.