[PATCH V2 3/3] OMAPDSS: DISPC: Correct DISPC functional clock usage

DISPC_FCLK is incorrectly used as functional clock of DISPC in scaling
calculations. So, DISPC_CORE_CLK replaces as functional clock of DISPC.
DISPC_CORE_CLK is derived from DISPC_FCLK divided by an independent DISPC
divisor LCD.

Signed-off-by: Chandrabhanu Mahapatra <redacted>
---
 drivers/video/omap2/dss/dispc.c |   13 +++++++------
 1 files changed, 7 insertions(+), 6 deletions(-)

diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
index d8a1672..1fdac73 100644
--- a/drivers/video/omap2/dss/dispc.c
+++ b/drivers/video/omap2/dss/dispc.c

@@ -1761,6 +1761,7 @@ static int dispc_ovl_calc_scaling(enum omap_plane plane,
 				dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
 	const int max_decim_limit = 16;
 	unsigned long fclk = 0;
+	unsigned long dispc_core_clk = dispc_mgr_lclk_rate(channel);
 	int decim_x, decim_y, error, min_factor;
 	u16 in_width, in_height, in_width_max = 0;
 

@@ -1803,7 +1804,7 @@ static int dispc_ovl_calc_scaling(enum omap_plane plane,
 			fclk = calc_fclk(channel, in_width, in_height,
 					out_width, out_height);
 			error = (in_width > maxsinglelinewidth || !fclk ||
-				fclk > dispc_fclk_rate());
+				fclk > dispc_core_clk);
 			if (error) {
 				if (decim_x = decim_y) {
 					decim_x = min_factor;

@@ -1841,7 +1842,7 @@ static int dispc_ovl_calc_scaling(enum omap_plane plane,
 					out_width, out_height);
 			error = (error || in_width > maxsinglelinewidth * 2 ||
 				(in_width > maxsinglelinewidth && *five_taps) ||
-				!fclk || fclk > dispc_fclk_rate());
+				!fclk || fclk > dispc_core_clk);
 			if (error) {
 				if (decim_x = decim_y) {
 					decim_x = min_factor;

@@ -1873,7 +1874,7 @@ static int dispc_ovl_calc_scaling(enum omap_plane plane,
 		}
 	} else {
 		in_height = DIV_ROUND_UP(height, decim_y);
-		in_width_max = dispc_fclk_rate() /
+		in_width_max = dispc_core_clk /
 				DIV_ROUND_UP(dispc_mgr_pclk_rate(channel),
 						out_width);
 		decim_x = DIV_ROUND_UP(width, in_width_max);

@@ -1894,13 +1895,13 @@ static int dispc_ovl_calc_scaling(enum omap_plane plane,
 	}
 
 	DSSDBG("required fclk rate = %lu Hz\n", fclk);
-	DSSDBG("current fclk rate = %lu Hz\n", dispc_fclk_rate());
+	DSSDBG("current fclk rate = %lu Hz\n", dispc_core_clk);
 
-	if (!fclk || fclk > dispc_fclk_rate()) {
+	if (!fclk || fclk > dispc_core_clk) {
 		DSSERR("failed to set up scaling, "
 			"required fclk rate = %lu Hz, "
 			"current fclk rate = %lu Hz\n",
-			fclk, dispc_fclk_rate());
+			fclk, dispc_core_clk);
 		return -EINVAL;
 	}
 

-- 
1.7.1

On Wed, 2012-03-21 at 15:22 +0530, Chandrabhanu Mahapatra wrote:

Hmm, I don't think this is correct. dispc_mgr_lclk_rate() returns the
logic clock for the LCD output path. It's not DISPC core clock.

 Tomi

On Tue, Mar 27, 2012 at 4:33 PM, Tomi Valkeinen [off-list ref] wrote:

On Wed, 2012-03-21 at 15:22 +0530, Chandrabhanu Mahapatra wrote:

quoted

DISPC_FCLK is incorrectly used as functional clock of DISPC in scaling
calculations. So, DISPC_CORE_CLK replaces as functional clock of DISPC.
DISPC_CORE_CLK is derived from DISPC_FCLK divided by an independent DISPC
divisor LCD.

Signed-off-by: Chandrabhanu Mahapatra <redacted>
---
 drivers/video/omap2/dss/dispc.c |   13 +++++++------
 1 files changed, 7 insertions(+), 6 deletions(-)

diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
index d8a1672..1fdac73 100644
--- a/drivers/video/omap2/dss/dispc.c
+++ b/drivers/video/omap2/dss/dispc.c

@@ -1761,6 +1761,7 @@ static int dispc_ovl_calc_scaling(enum omap_plane plane,

                              dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
      const int max_decim_limit = 16;
      unsigned long fclk = 0;
+     unsigned long dispc_core_clk = dispc_mgr_lclk_rate(channel);

Hmm, I don't think this is correct. dispc_mgr_lclk_rate() returns the
logic clock for the LCD output path. It's not DISPC core clock.

 Tomi

As per the OMAP4 TRM DISPC_CORE_CLK is DISPC_FCLK / LCD factor and
dispc_mgr_lclk_rate() exactly does the same. Should we rename the
function or have a separate fucntion for dispc_core_clk to avoid
confusion?

-- 
Chandrabhanu Mahapatra
Texas Instruments India Pvt. Ltd.

On Tue, 2012-03-27 at 16:44 +0530, Mahapatra, Chandrabhanu wrote:

On Tue, Mar 27, 2012 at 4:33 PM, Tomi Valkeinen [off-list ref] wrote:

quoted

On Wed, 2012-03-21 at 15:22 +0530, Chandrabhanu Mahapatra wrote:

quoted

DISPC_FCLK is incorrectly used as functional clock of DISPC in scaling
calculations. So, DISPC_CORE_CLK replaces as functional clock of DISPC.
DISPC_CORE_CLK is derived from DISPC_FCLK divided by an independent DISPC
divisor LCD.

Signed-off-by: Chandrabhanu Mahapatra <redacted>
---
 drivers/video/omap2/dss/dispc.c |   13 +++++++------
 1 files changed, 7 insertions(+), 6 deletions(-)

diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
index d8a1672..1fdac73 100644
--- a/drivers/video/omap2/dss/dispc.c
+++ b/drivers/video/omap2/dss/dispc.c

@@ -1761,6 +1761,7 @@ static int dispc_ovl_calc_scaling(enum omap_plane plane,
                              dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
      const int max_decim_limit = 16;
      unsigned long fclk = 0;
+     unsigned long dispc_core_clk = dispc_mgr_lclk_rate(channel);

Hmm, I don't think this is correct. dispc_mgr_lclk_rate() returns the
logic clock for the LCD output path. It's not DISPC core clock.

 Tomi

As per the OMAP4 TRM DISPC_CORE_CLK is DISPC_FCLK / LCD factor and

Hmm? No it isn't. DISPC_CORE_CLK is DISPC_FCLK / LCD, where LCD is
defined in DISPC_DIVISOR register.

dispc_mgr_lclk_rate() returns the logic clock of an output, which is
LCD1_CLK / LCD1 or LCD2_CLK / LCD2. And LCD1 and LCD2 are defined in
DISPC_DIVISORo(n) register.

(Very confusing to have LCD mean a liquid-crystal-display and also
logic-clock-divisor =) I think we should rename them. Perhaps LCKD and
PCKD).

So the clocks for DISPC and for LCD outputs are totally separate ones,
on OMAP4. For OMAP2/3 they are the same.

That said, I have no idea which of the clock is used for what regarding
scaling calculations, and even less do I know how it's managed for
TV-out...

dispc_mgr_lclk_rate() exactly does the same. Should we rename the
function or have a separate fucntion for dispc_core_clk to avoid
confusion?

I think we definitely should have a separate function, as it's a
separate clock. And I guess the places where FCKs and LCKs are used
should be verified so that they use the correct one. If somebody knows
what is the correct one (the TRM is a bit vague at times =).

 Tomi