[PATCH 2/5] pxafb: allow better platform configurable smart panel timing
DORMANTno replies
From: Eric Miao <hidden>
Date: 2008-12-11 09:47:29
Subsystem:
framebuffer layer, the rest · Maintainers:
Helge Deller, Linus Torvalds
For smart panels (LCD panel with internal framebuffer), the following
LCCR3 register bits have different meanings than the parallel one:
LCCR3_PCP - controls the L_PCLK_WR polarity
LCCR3_HSP - controls the L_LCLK_A0 polarity
LCCR3_VSP - controls the L_FCLK_RD polarity
To keep minimum change to the original parallel timing, the .lcd_conn
flags and 'pxafb_mode_info.sync' are re-used to reflect this:
LCD_PCLK_EDGE_{RISE,FALL} - configures LCCR3_PCP
sync & FB_SYNC_{HOR,VERT}_HIGH_ACT - configures LCCR3_{HSP,VSP}
Signed-off-by: Eric Miao <redacted>
---
arch/arm/mach-pxa/include/mach/pxafb.h | 4 ++++
drivers/video/pxafb.c | 4 +++-
2 files changed, 7 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-pxa/include/mach/pxafb.hb/arch/arm/mach-pxa/include/mach/pxafb.h index cb44410..4201a88 100644
--- a/arch/arm/mach-pxa/include/mach/pxafb.h
+++ b/arch/arm/mach-pxa/include/mach/pxafb.h@@ -95,6 +95,10 @@ struct pxafb_mode_info { * in pxa27x and pxa3xx, initialize them to the same value or * the larger one will be used * 3. same to {rd,wr}_pulse_width + * + * 4. LCD_PCLK_EDGE_{RISE,FALL} controls the L_PCLK_WR polarity + * 5. sync & FB_SYNC_HOR_HIGH_ACT controls the L_LCLK_A0 + * 6. sync & FB_SYNC_VERT_HIGH_ACT controls the L_LCLK_RD */ unsigned a0csrd_set_hld; /* A0 and CS Setup/Hold Time before/after
L_FCLK_RD */ unsigned a0cswr_set_hld; /* A0 and CS Setup/Hold Time before/after L_PCLK_WR */
diff --git a/drivers/video/pxafb.c b/drivers/video/pxafb.c
index e0bba02..c082547 100644
--- a/drivers/video/pxafb.c
+++ b/drivers/video/pxafb.c@@ -760,7 +760,9 @@ static void setup_smart_timing(struct pxafb_info *fbi, LCCR1_HorSnchWdth(__smart_timing(t3, lclk)); fbi->reg_lccr2 = LCCR2_DisHght(var->yres); - fbi->reg_lccr3 = LCCR3_PixClkDiv(__smart_timing(t4, lclk)); + fbi->reg_lccr3 = fbi->lccr3 | LCCR3_PixClkDiv(__smart_timing(t4, lclk)); + fbi->reg_lccr3 |= (var->sync & FB_SYNC_HOR_HIGH_ACT) ? LCCR3_HSP : 0; + fbi->reg_lccr3 |= (var->sync & FB_SYNC_VERT_HIGH_ACT) ? LCCR3_VSP : 0; /* FIXME: make this configurable */ fbi->reg_cmdcr = 1;
--
1.6.0.4
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