[PATCH 3/4] cirrusfb: fix 16bpp modes
DORMANTno replies
From: Krzysztof Helt <hidden>
Date: 2008-09-05 21:46:34
Subsystem:
framebuffer layer, the rest · Maintainers:
Helge Deller, Linus Torvalds
From: Krzysztof Helt <redacted> The 16bpp mode did not work on the Cirrus cards as the visual type was set to DIRECTCOLOR instead of TRUECOLOR. The Alpine family used one incorrect register setting so this 16bpp modes generated wrong horizontal frequency. Signed-off-by: Krzysztof Helt <redacted> --- I think it is not worth to push it into 2.6.27. This is an old error. drivers/video/cirrusfb.c | 7 ++----- 1 files changed, 2 insertions(+), 5 deletions(-)
diff --git a/drivers/video/cirrusfb.c b/drivers/video/cirrusfb.c
index 245005e..9e0a1c5 100644
--- a/drivers/video/cirrusfb.c
+++ b/drivers/video/cirrusfb.c@@ -657,7 +657,7 @@ static int cirrusfb_decode_var(const struct fb_var_screeninfo *var, case 16: case 32: info->fix.line_length = var->xres_virtual * maxclockidx; - info->fix.visual = FB_VISUAL_DIRECTCOLOR; + info->fix.visual = FB_VISUAL_TRUECOLOR; break; default:
@@ -1178,10 +1178,7 @@ static int cirrusfb_set_par_foo(struct fb_info *info) case BT_ALPINE: DPRINTK(" (for GD543x)\n"); - if (var->xres >= 1024) - vga_wseq(regbase, CL_SEQR7, 0xa7); - else - vga_wseq(regbase, CL_SEQR7, 0xa3); + vga_wseq(regbase, CL_SEQR7, 0xa7); cirrusfb_set_mclk(cinfo, regs.mclk, regs.divMCLK); break;
--
1.5.2.2
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