# \[PATCH v22 8/8\] x86/vdso: Add ENDBR64 to \_\_vdso\_sgx\_enter\_enclave

- From: Yu-cheng Yu \<hidden\>
- Date: 2021-03-10 22:06:29 
- List: linux-doc
- Page: https://ratatoskr.run/linux-doc/2021/03/6295917
- Thread: https://ratatoskr.run/linux-doc/2021/03/6295910/t.md

```text
When CET is enabled, __vdso_sgx_enter_enclave() needs an endbr64
in the beginning of the function.

Signed-off-by: Yu-cheng Yu <redacted>
Cc: Andy Lutomirski <luto@kernel.org>
Cc: Dave Hansen <dave.hansen@linux.intel.com>
Cc: Jarkko Sakkinen <jarkko@kernel.org>
---
 arch/x86/entry/vdso/vsgx.S | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/x86/entry/vdso/vsgx.S b/arch/x86/entry/vdso/vsgx.S
index 86a0e94f68df..a70d4d09f713 100644
--- a/arch/x86/entry/vdso/vsgx.S
+++ b/arch/x86/entry/vdso/vsgx.S
@@ -27,6 +27,9 @@
 SYM_FUNC_START(__vdso_sgx_enter_enclave)
 	/* Prolog */
 	.cfi_startproc
+#ifdef CONFIG_X86_CET
+	endbr64
+#endif
 	push	%rbp
 	.cfi_adjust_cfa_offset	8
 	.cfi_rel_offset		%rbp, 0
-- 
2.21.0

```