--- v11
+++ v3
@@ -1,79 +1,179 @@
-*-internal-delay-ps properties would be applicable only for RGMII interface
-modes.
-
-It is changed as per the request,
-https://lore.kernel.org/netdev/d8e5f6a8-a7e1-dabd-f4b4-ea8ea21d0a1d@gmail.com/
-
-Ran dt_binding_check to confirm nothing is broken.
+Documentation in .yaml format and updates to the MAINTAINERS
+Also 'make dt_binding_check' is passed
Signed-off-by: Prasanna Vengateshan <prasanna.vengateshan@microchip.com>
-Reviewed-by: Andrew Lunn <andrew@lunn.ch>
---
- .../bindings/net/ethernet-controller.yaml | 37 +++++++++++++------
- 1 file changed, 25 insertions(+), 12 deletions(-)
+ .../bindings/net/dsa/microchip,lan937x.yaml | 148 ++++++++++++++++++
+ MAINTAINERS | 1 +
+ 2 files changed, 149 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/net/dsa/microchip,lan937x.yaml
-diff --git a/Documentation/devicetree/bindings/net/ethernet-controller.yaml b/Documentation/devicetree/bindings/net/ethernet-controller.yaml
-index 34c5463abcec..dc86a6479a86 100644
---- a/Documentation/devicetree/bindings/net/ethernet-controller.yaml
-+++ b/Documentation/devicetree/bindings/net/ethernet-controller.yaml
-@@ -123,12 +123,6 @@ properties:
- and is useful for determining certain configuration settings
- such as flow control thresholds.
-
-- rx-internal-delay-ps:
-- description: |
-- RGMII Receive Clock Delay defined in pico seconds.
-- This is used for controllers that have configurable RX internal delays.
-- If this property is present then the MAC applies the RX delay.
--
- sfp:
- $ref: /schemas/types.yaml#/definitions/phandle
- description:
-@@ -140,12 +134,6 @@ properties:
- The size of the controller\'s transmit fifo in bytes. This
- is used for components that can have configurable fifo sizes.
-
-- tx-internal-delay-ps:
-- description: |
-- RGMII Transmit Clock Delay defined in pico seconds.
-- This is used for controllers that have configurable TX internal delays.
-- If this property is present then the MAC applies the TX delay.
--
- managed:
- description:
- Specifies the PHY management type. If auto is set and fixed-link
-@@ -222,6 +210,31 @@ properties:
- required:
- - speed
-
+diff --git a/Documentation/devicetree/bindings/net/dsa/microchip,lan937x.yaml b/Documentation/devicetree/bindings/net/dsa/microchip,lan937x.yaml
+new file mode 100644
+index 000000000000..69021117d595
+--- /dev/null
++++ b/Documentation/devicetree/bindings/net/dsa/microchip,lan937x.yaml
+@@ -0,0 +1,148 @@
++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/net/dsa/microchip,lan937x.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: LAN937x Ethernet Switch Series Tree Bindings
++
++maintainers:
++ - UNGLinuxDriver@microchip.com
++
+allOf:
-+ - if:
-+ properties:
-+ phy-mode:
-+ contains:
-+ enum:
-+ - rgmii
-+ - rgmii-rxid
-+ - rgmii-txid
-+ - rgmii-id
-+ then:
-+ properties:
-+ rx-internal-delay-ps:
-+ description:
-+ RGMII Receive Clock Delay defined in pico seconds.This is
-+ used for controllers that have configurable RX internal
-+ delays. If this property is present then the MAC applies
-+ the RX delay.
-+ tx-internal-delay-ps:
-+ description:
-+ RGMII Transmit Clock Delay defined in pico seconds.This is
-+ used for controllers that have configurable TX internal
-+ delays. If this property is present then the MAC applies
-+ the TX delay.
++ - $ref: dsa.yaml#
+
- additionalProperties: true
-
- ...
++properties:
++ compatible:
++ enum:
++ - microchip,lan9370
++ - microchip,lan9371
++ - microchip,lan9372
++ - microchip,lan9373
++ - microchip,lan9374
++
++ reg:
++ maxItems: 1
++
++ spi-max-frequency:
++ maximum: 50000000
++
++ reset-gpios:
++ description: Optional gpio specifier for a reset line
++ maxItems: 1
++
++required:
++ - compatible
++ - reg
++
++unevaluatedProperties: false
++
++examples:
++ - |
++ #include <dt-bindings/gpio/gpio.h>
++
++ //Ethernet switch connected via spi to the host
++ ethernet {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ fixed-link {
++ speed = <1000>;
++ full-duplex;
++ };
++ };
++
++ spi {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ lan9374: switch@0 {
++ compatible = "microchip,lan9374";
++ reg = <0>;
++
++ spi-max-frequency = <44000000>;
++
++ ethernet-ports {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ port@0 {
++ reg = <0>;
++ label = "lan1";
++ phy-mode = "internal";
++ phy-handle = <&t1phy0>;
++ };
++ port@1 {
++ reg = <1>;
++ label = "lan2";
++ phy-mode = "internal";
++ phy-handle = <&t1phy1>;
++ };
++ port@2 {
++ reg = <2>;
++ label = "lan4";
++ phy-mode = "internal";
++ phy-handle = <&t1phy2>;
++ };
++ port@3 {
++ reg = <3>;
++ label = "lan6";
++ phy-mode = "internal";
++ phy-handle = <&t1phy3>;
++ };
++ port@4 {
++ reg = <4>;
++ phy-mode = "rgmii";
++ ethernet = <ðernet>;
++ fixed-link {
++ speed = <1000>;
++ full-duplex;
++ };
++ };
++ port@5 {
++ reg = <5>;
++ label = "lan7";
++ phy-mode = "rgmii";
++ fixed-link {
++ speed = <1000>;
++ full-duplex;
++ };
++ };
++ port@6 {
++ reg = <6>;
++ label = "lan5";
++ phy-mode = "internal";
++ phy-handle = <&t1phy4>;
++ };
++ port@7 {
++ reg = <7>;
++ label = "lan3";
++ phy-mode = "internal";
++ phy-handle = <&t1phy5>;
++ };
++ };
++
++ mdio {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ t1phy0: ethernet-phy@0{
++ reg = <0x0>;
++ };
++ t1phy1: ethernet-phy@1{
++ reg = <0x1>;
++ };
++ t1phy2: ethernet-phy@2{
++ reg = <0x2>;
++ };
++ t1phy3: ethernet-phy@3{
++ reg = <0x3>;
++ };
++ t1phy4: ethernet-phy@6{
++ reg = <0x6>;
++ };
++ t1phy5: ethernet-phy@7{
++ reg = <0x7>;
++ };
++ };
++ };
++ };
+diff --git a/MAINTAINERS b/MAINTAINERS
+index da478d5c8b0c..f0ce2378b681 100644
+--- a/MAINTAINERS
++++ b/MAINTAINERS
+@@ -12181,6 +12181,7 @@ M: UNGLinuxDriver@microchip.com
+ L: netdev@vger.kernel.org
+ S: Maintained
+ F: Documentation/devicetree/bindings/net/dsa/microchip,ksz.yaml
++F: Documentation/devicetree/bindings/net/dsa/microchip,lan937x.yaml
+ F: drivers/net/dsa/microchip/*
+ F: include/linux/platform_data/microchip-ksz.h
+ F: net/dsa/tag_ksz.c
--
-2.30.2
+2.27.0