[PATCH 4/4] soc: sifive: ccache: Support cache management operations
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From: <hidden>
Date: 2023-10-25 18:56:56
Also in:
linux-riscv, lkml
This cache controller also supports flushing cache lines by writing their address to a register. This can be used for cache management on SoCs with non-coherent DMAs that predate the RISC-V Zicbom extension such as the StarFive JH7100 SoC. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> --- drivers/soc/sifive/sifive_ccache.c | 45 +++++++++++++++++++++++++++++- 1 file changed, 44 insertions(+), 1 deletion(-)
diff --git a/drivers/soc/sifive/sifive_ccache.cb/drivers/soc/sifive/sifive_ccache.c index 676468c35859..9bf94c22cad9 100644
--- a/drivers/soc/sifive/sifive_ccache.c
+++ b/drivers/soc/sifive/sifive_ccache.c@@ -8,13 +8,16 @@ #define pr_fmt(fmt) "CCACHE: " fmt +#include <linux/align.h> #include <linux/debugfs.h> #include <linux/interrupt.h> #include <linux/of_irq.h> #include <linux/of_address.h> #include <linux/device.h> #include <linux/bitfield.h> +#include <asm/cacheflush.h> #include <asm/cacheinfo.h> +#include <asm/dma-noncoherent.h> #include <soc/sifive/sifive_ccache.h> #define SIFIVE_CCACHE_DIRECCFIX_LOW 0x100
@@ -39,10 +42,14 @@ #define SIFIVE_CCACHE_CONFIG_SETS_MASK GENMASK_ULL(23, 16) #define SIFIVE_CCACHE_CONFIG_BLKS_MASK GENMASK_ULL(31, 24) +#define SIFIVE_CCACHE_FLUSH64 0x200 +#define SIFIVE_CCACHE_FLUSH32 0x240 + #define SIFIVE_CCACHE_WAYENABLE 0x08 #define SIFIVE_CCACHE_ECCINJECTERR 0x40 #define SIFIVE_CCACHE_MAX_ECCINTR 4 +#define SIFIVE_CCACHE_LINE_SIZE 64 static void __iomem *ccache_base; static int g_irq[SIFIVE_CCACHE_MAX_ECCINTR];
@@ -125,6 +132,34 @@ intunregister_sifive_ccache_error_notifier(struct notifier_block *nb)
}
EXPORT_SYMBOL_GPL(unregister_sifive_ccache_error_notifier);
+#ifdef CONFIG_RISCV_NONSTANDARD_CACHE_OPS
+static void ccache_flush_range(phys_addr_t start, size_t len)
+{
+ phys_addr_t end = start + len;
+ phys_addr_t line;
+
+ if (!len)
+ return;
+
+ mb();
+ for (line = ALIGN_DOWN(start, SIFIVE_CCACHE_LINE_SIZE); line < end;
+ line += SIFIVE_CCACHE_LINE_SIZE) {
+#ifdef CONFIG_32BIT
+ writel(line >> 4, ccache_base + SIFIVE_CCACHE_FLUSH32);
+#else
+ writeq(line, ccache_base + SIFIVE_CCACHE_FLUSH64);
+#endif
+ mb();
+ }
+}
+
+static const struct riscv_nonstd_cache_ops ccache_mgmt_ops __initdata = {
+ .wback = &ccache_flush_range,
+ .inv = &ccache_flush_range,
+ .wback_inv = &ccache_flush_range,
+};
+#endif /* CONFIG_RISCV_NONSTANDARD_CACHE_OPS */
+
static int ccache_largest_wayenabled(void)
{
return readl(ccache_base + SIFIVE_CCACHE_WAYENABLE) & 0xFF;@@ -258,6 +293,14 @@ static int __init sifive_ccache_init(void) } of_node_put(np); +#ifdef CONFIG_RISCV_NONSTANDARD_CACHE_OPS + if (of_property_read_bool(np, "sifive,cache-ops")) { + riscv_cbom_block_size = SIFIVE_CCACHE_LINE_SIZE; + riscv_noncoherent_supported(); + riscv_noncoherent_register_cache_ops(&ccache_mgmt_ops); + } +#endif + ccache_config_read(); ccache_cache_ops.get_priv_group = ccache_get_priv_group;
@@ -278,4 +321,4 @@ static int __init sifive_ccache_init(void) return rc; } -device_initcall(sifive_ccache_init); +arch_initcall(sifive_ccache_init);
--
2.40.1