@@ -0,0 +1,73 @@+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause+%YAML1.2+---+$id:http://devicetree.org/schemas/mtd/cadence,nand.yaml#+$schema:http://devicetree.org/meta-schemas/core.yaml#++title:Cadence NAND controller++maintainers:+-Niravkumar L Rabara <niravkumar.l.rabara@intel.com>++allOf:+-$ref:nand-controller.yaml++properties:+compatible:+items:+-const:cdns,hp-nfc++reg:+items:+-description:Address and length of the controller register set+-description:Address and length of the Slave DMA data port++reg-names:+items:+-const:reg+-const:sdma++interrupts:+maxItems:1++clocks:+maxItems:1++dmas:+maxItems:1++cdns,board-delay-ps:+description:|+Estimated Board delay. The value includes the total round trip+delay for the signals and is used for deciding on values associated+with data read capture. The example formula for SDR mode is the+following.+board delay = RE#PAD delay + PCB trace to device + PCB trace from device++ DQ PAD delay++required:+-compatible+-reg+-reg-names+-interrupts+-clocks++unevaluatedProperties:false++examples:+-|+nand-controller@10b80000 {+compatible = "cdns,hp-nfc";+reg = <0x10b80000 0x10000>,+<0x10840000 0x10000>;+reg-names = "reg", "sdma";+#address-cells = <1>;+#size-cells = <0>;+interrupts = <0 97 4>;+clocks = <&nf_clk>;+cdns,board-delay-ps = <4830>;++nand@0 {+reg = <0>;+};+};
@@ -1,53 +0,0 @@-* Cadence NAND controller--Required properties:- - compatible : "cdns,hp-nfc"- - reg : Contains two entries, each of which is a tuple consisting of a- physical address and length. The first entry is the address and- length of the controller register set. The second entry is the- address and length of the Slave DMA data port.- - reg-names: should contain "reg" and "sdma"- - #address-cells: should be 1. The cell encodes the chip select connection.- - #size-cells : should be 0.- - interrupts : The interrupt number.- - clocks: phandle of the controller core clock (nf_clk).--Optional properties:- - dmas: shall reference DMA channel associated to the NAND controller- - cdns,board-delay-ps : Estimated Board delay. The value includes the total- round trip delay for the signals and is used for deciding on values- associated with data read capture. The example formula for SDR mode is- the following:- board delay = RE#PAD delay + PCB trace to device + PCB trace from device- + DQ PAD delay--Child nodes represent the available NAND chips.--Required properties of NAND chips:- - reg: shall contain the native Chip Select ids from 0 to max supported by- the cadence nand flash controller--See Documentation/devicetree/bindings/mtd/nand-controller.yaml for more details on-generic bindings.--Example:--nand_controller: nand-controller@60000000 {- compatible = "cdns,hp-nfc";- #address-cells = <1>;- #size-cells = <0>;- reg = <0x60000000 0x10000>, <0x80000000 0x10000>;- reg-names = "reg", "sdma";- clocks = <&nf_clk>;- cdns,board-delay-ps = <4830>;- interrupts = <2 0>;- nand@0 {- reg = <0>;- label = "nand-1";- };- nand@1 {- reg = <1>;- label = "nand-2";- };--};
@@ -0,0 +1,73 @@+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause+%YAML1.2+---+$id:http://devicetree.org/schemas/mtd/cadence,nand.yaml#+$schema:http://devicetree.org/meta-schemas/core.yaml#++title:Cadence NAND controller++maintainers:+-Niravkumar L Rabara <niravkumar.l.rabara@intel.com>++allOf:+-$ref:nand-controller.yaml++properties:+compatible:+items:+-const:cdns,hp-nfc++reg:+items:+-description:Address and length of the controller register set+-description:Address and length of the Slave DMA data port++reg-names:+items:+-const:reg+-const:sdma++interrupts:+maxItems:1++clocks:+maxItems:1++dmas:+maxItems:1++cdns,board-delay-ps:+description:|+Estimated Board delay. The value includes the total round trip+delay for the signals and is used for deciding on values associated+with data read capture. The example formula for SDR mode is the+following.+board delay = RE#PAD delay + PCB trace to device + PCB trace from device++ DQ PAD delay++required:+-compatible+-reg+-reg-names+-interrupts+-clocks++unevaluatedProperties:false++examples:+-|+nand-controller@10b80000 {+compatible = "cdns,hp-nfc";+reg = <0x10b80000 0x10000>,+<0x10840000 0x10000>;+reg-names = "reg", "sdma";+#address-cells = <1>;+#size-cells = <0>;+interrupts = <0 97 4>;+clocks = <&nf_clk>;+cdns,board-delay-ps = <4830>;++nand@0 {+reg = <0>;+};+};
@@ -1,53 +0,0 @@-* Cadence NAND controller--Required properties:- - compatible : "cdns,hp-nfc"- - reg : Contains two entries, each of which is a tuple consisting of a- physical address and length. The first entry is the address and- length of the controller register set. The second entry is the- address and length of the Slave DMA data port.- - reg-names: should contain "reg" and "sdma"- - #address-cells: should be 1. The cell encodes the chip select connection.- - #size-cells : should be 0.- - interrupts : The interrupt number.- - clocks: phandle of the controller core clock (nf_clk).--Optional properties:- - dmas: shall reference DMA channel associated to the NAND controller- - cdns,board-delay-ps : Estimated Board delay. The value includes the total- round trip delay for the signals and is used for deciding on values- associated with data read capture. The example formula for SDR mode is- the following:- board delay = RE#PAD delay + PCB trace to device + PCB trace from device- + DQ PAD delay--Child nodes represent the available NAND chips.
This is not fully pictured in the current schema, by referencing
nand-controller.yaml I believe you allow all kind of direct
partitioning (which is legacy, and not supposed to be supported here).
Can you try to define a partition directly within the controller node
in the example and see whether it still passes the checks?
Thanks,
Miquèl
@@ -0,0 +1,73 @@+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause %YAML 1.2+---+$id:http://devicetree.org/schemas/mtd/cadence,nand.yaml#+$schema:http://devicetree.org/meta-schemas/core.yaml#++title:Cadence NAND controller++maintainers:+-Niravkumar L Rabara <niravkumar.l.rabara@intel.com>++allOf:+-$ref:nand-controller.yaml++properties:+compatible:+items:+-const:cdns,hp-nfc++reg:+items:+-description:Address and length of the controller register set+-description:Address and length of the Slave DMA data port++reg-names:+items:+-const:reg+-const:sdma++interrupts:+maxItems:1++clocks:+maxItems:1++dmas:+maxItems:1++cdns,board-delay-ps:+description:|+Estimated Board delay. The value includes the total round trip+delay for the signals and is used for deciding on values associated+with data read capture. The example formula for SDR mode is the+following.+board delay = RE#PAD delay + PCB trace to device + PCB trace from device++ DQ PAD delay++required:+-compatible+-reg+-reg-names+-interrupts+-clocks++unevaluatedProperties:false++examples:+-|+nand-controller@10b80000 {+compatible = "cdns,hp-nfc";+reg = <0x10b80000 0x10000>,+<0x10840000 0x10000>;+reg-names = "reg", "sdma";+#address-cells = <1>;+#size-cells = <0>;+interrupts = <0 97 4>;+clocks = <&nf_clk>;+cdns,board-delay-ps = <4830>;++nand@0 {+reg = <0>;+};+};
@@ -1,53 +0,0 @@-* Cadence NAND controller--Required properties:- - compatible : "cdns,hp-nfc"- - reg : Contains two entries, each of which is a tuple consisting of a- physical address and length. The first entry is the address and- length of the controller register set. The second entry is the- address and length of the Slave DMA data port.- - reg-names: should contain "reg" and "sdma"- - #address-cells: should be 1. The cell encodes the chip select connection.- - #size-cells : should be 0.- - interrupts : The interrupt number.- - clocks: phandle of the controller core clock (nf_clk).--Optional properties:- - dmas: shall reference DMA channel associated to the NAND
controller
- - cdns,board-delay-ps : Estimated Board delay. The value includes the total
- round trip delay for the signals and is used for deciding on values
- associated with data read capture. The example formula for SDR mode is
- the following:
- board delay = RE#PAD delay + PCB trace to device + PCB trace from device
- + DQ PAD delay
-
-Child nodes represent the available NAND chips.
This is not fully pictured in the current schema, by referencing nand-
controller.yaml I believe you allow all kind of direct partitioning (which is legacy,
and not supposed to be supported here).
Can you try to define a partition directly within the controller node in the example
and see whether it still passes the checks?
Thanks,
Miquèl
Hi Miquel,
I tried below in the controller node in example,
...
clocks = <&nf_clk>;
cdns,board-delay-ps = <4830>;
partition@0 {
label = "boot";
reg = <0 0x00200000>;
};
nand@0 {
reg = <0>;
};
It shows 'partition@0' was unexpected.
DTC_CHK Documentation/devicetree/bindings/mtd/cadence,nand.example.dtb
Documentation/devicetree/bindings/mtd/cadence,nand.example.dts:35.23-38.14: Warning (unique_unit_address_if_enabled): /example-0/nand-controller@10b80000/partition@0: duplicate unit-address (also used in node /example-0/nand-controller@10b80000/nand@0)
/mnt/newvolume/users/nrabara/kernel.org/3oct23/Documentation/devicetree/bindings/mtd/cadence,nand.example.dtb: nand-controller@10b80000: Unevaluated properties are not allowed ('partition@0' was unexpected)
From schema: /mnt/newvolume/users/nrabara/kernel.org/3oct23/Documentation/devicetree/bindings/mtd/cadence,nand.yaml
However using partition in nand node is OK.
nand@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "boot";
reg = <0 0x00200000>;
};
partition@200000 {
label = "env";
reg = <0x00200000 0x00400000>;
};
};
"make dt_binding_check DT_SCHEMA_FILES=mtd/cadence,nand.yaml" is OK without any warnings.
DTEX Documentation/devicetree/bindings/mtd/cadence,nand.example.dts
DTC_CHK Documentation/devicetree/bindings/mtd/cadence,nand.example.dtb
Any additional changes required for this patch?
Thanks,
Nirav
This is not fully pictured in the current schema, by referencing nand-
controller.yaml I believe you allow all kind of direct partitioning (which is legacy,
and not supposed to be supported here).
Can you try to define a partition directly within the controller node in the example
and see whether it still passes the checks?
Thanks,
Miquèl
Hi Miquel,
I tried below in the controller node in example,
...
clocks = <&nf_clk>;
cdns,board-delay-ps = <4830>;
partition@0 {
label = "boot";
reg = <0 0x00200000>;
};
nand@0 {
reg = <0>;
};
It shows 'partition@0' was unexpected.
DTC_CHK Documentation/devicetree/bindings/mtd/cadence,nand.example.dtb
Documentation/devicetree/bindings/mtd/cadence,nand.example.dts:35.23-38.14: Warning (unique_unit_address_if_enabled): /example-0/nand-controller@10b80000/partition@0: duplicate unit-address (also used in node /example-0/nand-controller@10b80000/nand@0)
/mnt/newvolume/users/nrabara/kernel.org/3oct23/Documentation/devicetree/bindings/mtd/cadence,nand.example.dtb: nand-controller@10b80000: Unevaluated properties are not allowed ('partition@0' was unexpected)
From schema: /mnt/newvolume/users/nrabara/kernel.org/3oct23/Documentation/devicetree/bindings/mtd/cadence,nand.yaml
However using partition in nand node is OK.
nand@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "boot";
reg = <0 0x00200000>;
};
partition@200000 {
label = "env";
reg = <0x00200000 0x00400000>;
};
};
"make dt_binding_check DT_SCHEMA_FILES=mtd/cadence,nand.yaml" is OK without any warnings.
DTEX Documentation/devicetree/bindings/mtd/cadence,nand.example.dts
DTC_CHK Documentation/devicetree/bindings/mtd/cadence,nand.example.dtb
Any additional changes required for this patch?