[PATCH 0/3] SM6115 LPASSCC

This series brings support for the LPASS clock controllers on the SM6115
and similar. It provides resets that need to be toggled as part of
soundwire bringup routines.

Signed-off-by: Konrad Dybcio <redacted>
---
Konrad Dybcio (3):
      dt-bindings: clock: Add Qualcomm SM6115 LPASS clock controller
      clk: qcom: reset: Increase max reset delay
      clk: qcom: Add SM6115 LPASSCC

 .../bindings/clock/qcom,sm6115-lpasscc.yaml        | 53 ++++++++++++++
 drivers/clk/qcom/Kconfig                           |  9 +++
 drivers/clk/qcom/Makefile                          |  1 +
 drivers/clk/qcom/lpasscc-sm6115.c                  | 84 ++++++++++++++++++++++
 drivers/clk/qcom/reset.h                           |  2 +-
 include/dt-bindings/clock/qcom,sm6115-lpasscc.h    | 15 ++++
 6 files changed, 163 insertions(+), 1 deletion(-)
---
base-commit: 6269320850097903b30be8f07a5c61d9f7592393
change-id: 20230825-topic-6115_lpasscc-02a4f5793acd

Best regards,
-- 
Konrad Dybcio [off-list ref]

SM6115 (and its derivatives or similar SoCs) have a LPASS clock
controller block which provides audio-related resets.

Add bindings for it.

Signed-off-by: Konrad Dybcio <redacted>
---
 .../bindings/clock/qcom,sm6115-lpasscc.yaml        | 53 ++++++++++++++++++++++
 include/dt-bindings/clock/qcom,sm6115-lpasscc.h    | 15 ++++++
 2 files changed, 68 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/qcom,sm6115-lpasscc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm6115-lpasscc.yaml
new file mode 100644
index 000000000000..58ee84aed073
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,sm6115-lpasscc.yaml

@@ -0,0 +1,53 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,sm6115-lpasscc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm LPASS Core & Audio Clock Controller on SM6115
+
+maintainers:
+  - Konrad Dybcio <konrad.dybcio@linaro.org>
+  - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
+
+description: |
+  Qualcomm LPASS core and audio clock controllers provide audio-related resets
+  on SM6115 and its derivatives.
+
+  See also::
+    include/dt-bindings/clock/qcom,sm6115-lpasscc.h
+
+properties:
+  compatible:
+    enum:
+      - qcom,sm6115-lpassaudiocc
+      - qcom,sm6115-lpasscc
+
+  reg:
+    maxItems: 1
+
+  '#reset-cells':
+    const: 1
+
+required:
+  - compatible
+  - reg
+  - '#reset-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+    lpass_audiocc: clock-controller@a6a9000 {
+        compatible = "qcom,sm6115-lpassaudiocc";
+        reg = <0x0a6a9000 0x1000>;
+        #reset-cells = <1>;
+    };
+
+  - |
+    lpasscc: clock-controller@a7ec000 {
+        compatible = "qcom,sm6115-lpasscc";
+        reg = <0x0a7ec000 0x1000>;
+        #reset-cells = <1>;
+    };
+...

diff --git a/include/dt-bindings/clock/qcom,sm6115-lpasscc.h b/include/dt-bindings/clock/qcom,sm6115-lpasscc.h
new file mode 100644
index 000000000000..799274517c9a
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,sm6115-lpasscc.h

@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2023, Linaro Ltd.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_LPASSCC_SM6115_H
+#define _DT_BINDINGS_CLK_QCOM_LPASSCC_SM6115_H
+
+/* LPASS CC */
+#define LPASS_SWR_TX_CONFIG_CGCR		0
+
+/* LPASS_AUDIO CC */
+#define LPASS_AUDIO_SWR_RX_CGCR			0
+
+#endif

-- 
2.42.0

u8 limits us to 255 microseconds of delay. Promote the delay variable to
u16 to hold bigger values.

Signed-off-by: Konrad Dybcio <redacted>
---
 drivers/clk/qcom/reset.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/qcom/reset.h b/drivers/clk/qcom/reset.h
index 9a47c838d9b1..fe0561bf53d4 100644
--- a/drivers/clk/qcom/reset.h
+++ b/drivers/clk/qcom/reset.h

@@ -11,7 +11,7 @@
 struct qcom_reset_map {
 	unsigned int reg;
 	u8 bit;
-	u8 udelay;
+	u16 udelay;
 	u32 bitmask;
 };
 

-- 
2.42.0

SM6115 (and its derivatives or similar SoCs) have a LPASS clock
controller block which provides audio-related resets.

Add the required code to support them.

Signed-off-by: Konrad Dybcio <redacted>
---
 drivers/clk/qcom/Kconfig          |  9 +++++
 drivers/clk/qcom/Makefile         |  1 +
 drivers/clk/qcom/lpasscc-sm6115.c | 84 +++++++++++++++++++++++++++++++++++++++
 3 files changed, 94 insertions(+)

diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index bd9bfb11b328..df9cf112e4b6 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig

@@ -1001,6 +1001,15 @@ config SM_GPUCC_8550
 	  Say Y if you want to support graphics controller devices and
 	  functionality such as 3D graphics.
 
+config SM_LPASSCC_6115
+	tristate "SM6115 Low Power Audio Subsystem (LPASS) Clock Controller"
+	depends on ARM64 || COMPILE_TEST
+	select SM_GCC_6115
+	help
+	  Support for the LPASS clock controller on SM6115 devices.
+	  Say Y if you want to toggle LPASS-adjacent resets within
+	  this clock controller to reset the LPASS subsystem.
+
 config SM_TCSRCC_8550
 	tristate "SM8550 TCSR Clock Controller"
 	depends on ARM64 || COMPILE_TEST

diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 4790c8cca426..61e3c72fe954 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile

@@ -128,6 +128,7 @@ obj-$(CONFIG_SM_GPUCC_8250) += gpucc-sm8250.o
 obj-$(CONFIG_SM_GPUCC_8350) += gpucc-sm8350.o
 obj-$(CONFIG_SM_GPUCC_8450) += gpucc-sm8450.o
 obj-$(CONFIG_SM_GPUCC_8550) += gpucc-sm8550.o
+obj-$(CONFIG_SM_LPASSCC_6115) += lpasscc-sm6115.o
 obj-$(CONFIG_SM_TCSRCC_8550) += tcsrcc-sm8550.o
 obj-$(CONFIG_SM_VIDEOCC_8150) += videocc-sm8150.o
 obj-$(CONFIG_SM_VIDEOCC_8250) += videocc-sm8250.o

diff --git a/drivers/clk/qcom/lpasscc-sm6115.c b/drivers/clk/qcom/lpasscc-sm6115.c
new file mode 100644
index 000000000000..6aa19e16c53b
--- /dev/null
+++ b/drivers/clk/qcom/lpasscc-sm6115.c

@@ -0,0 +1,84 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2022, 2023 Linaro Limited
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/err.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/regmap.h>
+
+#include <dt-bindings/clock/qcom,sm6115-lpasscc.h>
+
+#include "common.h"
+#include "reset.h"
+
+static const struct qcom_reset_map lpass_audiocc_sm6115_resets[] = {
+	[LPASS_AUDIO_SWR_RX_CGCR] =  { .reg = 0x98, .bit = 1, .udelay = 500 },
+};
+
+static struct regmap_config lpass_audiocc_sm6115_regmap_config = {
+	.reg_bits = 32,
+	.reg_stride = 4,
+	.val_bits = 32,
+	.name = "lpass-audio-csr",
+	.max_register = 0x1000,
+};
+
+static const struct qcom_cc_desc lpass_audiocc_sm6115_reset_desc = {
+	.config = &lpass_audiocc_sm6115_regmap_config,
+	.resets = lpass_audiocc_sm6115_resets,
+	.num_resets = ARRAY_SIZE(lpass_audiocc_sm6115_resets),
+};
+
+static const struct qcom_reset_map lpasscc_sm6115_resets[] = {
+	[LPASS_SWR_TX_CONFIG_CGCR] = { .reg = 0x100, .bit = 1, .udelay = 500 },
+};
+
+static struct regmap_config lpasscc_sm6115_regmap_config = {
+	.reg_bits = 32,
+	.reg_stride = 4,
+	.val_bits = 32,
+	.name = "lpass-tcsr",
+	.max_register = 0x1000,
+};
+
+static const struct qcom_cc_desc lpasscc_sm6115_reset_desc = {
+	.config = &lpasscc_sm6115_regmap_config,
+	.resets = lpasscc_sm6115_resets,
+	.num_resets = ARRAY_SIZE(lpasscc_sm6115_resets),
+};
+
+static const struct of_device_id lpasscc_sm6115_match_table[] = {
+	{
+		.compatible = "qcom,sm6115-lpassaudiocc",
+		.data = &lpass_audiocc_sm6115_reset_desc,
+	}, {
+		.compatible = "qcom,sm6115-lpasscc",
+		.data = &lpasscc_sm6115_reset_desc,
+	},
+	{ },
+};
+MODULE_DEVICE_TABLE(of, lpasscc_sm6115_match_table);
+
+static int lpasscc_sm6115_probe(struct platform_device *pdev)
+{
+	const struct qcom_cc_desc *desc = of_device_get_match_data(&pdev->dev);
+
+	return qcom_cc_probe_by_index(pdev, 0, desc);
+}
+
+static struct platform_driver lpasscc_sm6115_driver = {
+	.probe = lpasscc_sm6115_probe,
+	.driver = {
+		.name = "lpasscc-sm6115",
+		.of_match_table = lpasscc_sm6115_match_table,
+	},
+};
+
+module_platform_driver(lpasscc_sm6115_driver);
+
+MODULE_DESCRIPTION("QTI LPASSCC SM6115 Driver");
+MODULE_LICENSE("GPL");

-- 
2.42.0

On 25/08/2023 20:13, Konrad Dybcio wrote:

Everything here is almost the same as sc8280xp one, so this should be
added to sc8280xp. You cut some boilerplate and additional driver.

Best regards,
Krzysztof

On 25/08/2023 20:13, Konrad Dybcio wrote:

Everything here looks the same as sc8280xp, so this could be just added
there as enum. The overall LPASS block version is different, but the
resets/clock controller look similar, doesn't it?

Also second example is not really needed. The difference is only in the
compatible.


Best regards,
Krzysztof

On 26.08.2023 11:28, Krzysztof Kozlowski wrote:

On 25/08/2023 20:13, Konrad Dybcio wrote:

quoted

SM6115 (and its derivatives or similar SoCs) have a LPASS clock
controller block which provides audio-related resets.

Add bindings for it.

Signed-off-by: Konrad Dybcio <redacted>
---
 .../bindings/clock/qcom,sm6115-lpasscc.yaml        | 53 ++++++++++++++++++++++
 include/dt-bindings/clock/qcom,sm6115-lpasscc.h    | 15 ++++++
 2 files changed, 68 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/qcom,sm6115-lpasscc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm6115-lpasscc.yaml
new file mode 100644
index 000000000000..58ee84aed073
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,sm6115-lpasscc.yaml

@@ -0,0 +1,53 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,sm6115-lpasscc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm LPASS Core & Audio Clock Controller on SM6115

Everything here looks the same as sc8280xp, so this could be just added
there as enum. The overall LPASS block version is different, but the
resets/clock controller look similar, doesn't it?

I think the 6115 cc block is a bit different, 8280 has more swr
hosts. Maybe Srini would know more.

[...]

Also second example is not really needed. The difference is only in the
compatible.

Ack

Konrad

On 26/08/2023 11:39, Konrad Dybcio wrote:

On 26.08.2023 11:28, Krzysztof Kozlowski wrote:

quoted

On 25/08/2023 20:13, Konrad Dybcio wrote:

quoted

SM6115 (and its derivatives or similar SoCs) have a LPASS clock
controller block which provides audio-related resets.

Add bindings for it.

Signed-off-by: Konrad Dybcio <redacted>
---
 .../bindings/clock/qcom,sm6115-lpasscc.yaml        | 53 ++++++++++++++++++++++
 include/dt-bindings/clock/qcom,sm6115-lpasscc.h    | 15 ++++++
 2 files changed, 68 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/qcom,sm6115-lpasscc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm6115-lpasscc.yaml
new file mode 100644
index 000000000000..58ee84aed073
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,sm6115-lpasscc.yaml

@@ -0,0 +1,53 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,sm6115-lpasscc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm LPASS Core & Audio Clock Controller on SM6115

Everything here looks the same as sc8280xp, so this could be just added
there as enum. The overall LPASS block version is different, but the
resets/clock controller look similar, doesn't it?

I think the 6115 cc block is a bit different, 8280 has more swr
hosts. Maybe Srini would know more.

Indeed, looking at downstream DTS this is closer to SM8250 and SM8350
than SC8280xp, with some interesting differences. But if you bring it
up, you also might fix SM8350, to which I looked a bit but then gave up.

Anyway, with the example staying or removed:

Reviewed-by: Krzysztof Kozlowski <redacted>

Best regards,
Krzysztof

On Sat, 26 Aug 2023 at 12:23, Krzysztof Kozlowski
[off-list ref] wrote:

On 25/08/2023 20:13, Konrad Dybcio wrote:

quoted

SM6115 (and its derivatives or similar SoCs) have a LPASS clock
controller block which provides audio-related resets.

Add the required code to support them.

Signed-off-by: Konrad Dybcio <redacted>
---
 drivers/clk/qcom/Kconfig          |  9 +++++
 drivers/clk/qcom/Makefile         |  1 +
 drivers/clk/qcom/lpasscc-sm6115.c | 84 +++++++++++++++++++++++++++++++++++++++
 3 files changed, 94 insertions(+)

diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index bd9bfb11b328..df9cf112e4b6 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig

@@ -1001,6 +1001,15 @@ config SM_GPUCC_8550
        Say Y if you want to support graphics controller devices and
        functionality such as 3D graphics.

+config SM_LPASSCC_6115
+     tristate "SM6115 Low Power Audio Subsystem (LPASS) Clock Controller"
+     depends on ARM64 || COMPILE_TEST
+     select SM_GCC_6115
+     help
+       Support for the LPASS clock controller on SM6115 devices.
+       Say Y if you want to toggle LPASS-adjacent resets within
+       this clock controller to reset the LPASS subsystem.
+
 config SM_TCSRCC_8550
      tristate "SM8550 TCSR Clock Controller"
      depends on ARM64 || COMPILE_TEST

diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 4790c8cca426..61e3c72fe954 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile

@@ -128,6 +128,7 @@ obj-$(CONFIG_SM_GPUCC_8250) += gpucc-sm8250.o
 obj-$(CONFIG_SM_GPUCC_8350) += gpucc-sm8350.o
 obj-$(CONFIG_SM_GPUCC_8450) += gpucc-sm8450.o
 obj-$(CONFIG_SM_GPUCC_8550) += gpucc-sm8550.o
+obj-$(CONFIG_SM_LPASSCC_6115) += lpasscc-sm6115.o
 obj-$(CONFIG_SM_TCSRCC_8550) += tcsrcc-sm8550.o
 obj-$(CONFIG_SM_VIDEOCC_8150) += videocc-sm8150.o
 obj-$(CONFIG_SM_VIDEOCC_8250) += videocc-sm8250.o

diff --git a/drivers/clk/qcom/lpasscc-sm6115.c b/drivers/clk/qcom/lpasscc-sm6115.c
new file mode 100644
index 000000000000..6aa19e16c53b
--- /dev/null
+++ b/drivers/clk/qcom/lpasscc-sm6115.c

@@ -0,0 +1,84 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2022, 2023 Linaro Limited
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/err.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/regmap.h>
+
+#include <dt-bindings/clock/qcom,sm6115-lpasscc.h>
+
+#include "common.h"
+#include "reset.h"
+
+static const struct qcom_reset_map lpass_audiocc_sm6115_resets[] = {
+     [LPASS_AUDIO_SWR_RX_CGCR] =  { .reg = 0x98, .bit = 1, .udelay = 500 },
+};
+
+static struct regmap_config lpass_audiocc_sm6115_regmap_config = {
+     .reg_bits = 32,
+     .reg_stride = 4,
+     .val_bits = 32,
+     .name = "lpass-audio-csr",
+     .max_register = 0x1000,
+};
+
+static const struct qcom_cc_desc lpass_audiocc_sm6115_reset_desc = {
+     .config = &lpass_audiocc_sm6115_regmap_config,
+     .resets = lpass_audiocc_sm6115_resets,
+     .num_resets = ARRAY_SIZE(lpass_audiocc_sm6115_resets),
+};
+
+static const struct qcom_reset_map lpasscc_sm6115_resets[] = {
+     [LPASS_SWR_TX_CONFIG_CGCR] = { .reg = 0x100, .bit = 1, .udelay = 500 },
+};
+
+static struct regmap_config lpasscc_sm6115_regmap_config = {
+     .reg_bits = 32,
+     .reg_stride = 4,
+     .val_bits = 32,
+     .name = "lpass-tcsr",
+     .max_register = 0x1000,
+};
+
+static const struct qcom_cc_desc lpasscc_sm6115_reset_desc = {
+     .config = &lpasscc_sm6115_regmap_config,
+     .resets = lpasscc_sm6115_resets,
+     .num_resets = ARRAY_SIZE(lpasscc_sm6115_resets),
+};
+
+static const struct of_device_id lpasscc_sm6115_match_table[] = {
+     {
+             .compatible = "qcom,sm6115-lpassaudiocc",
+             .data = &lpass_audiocc_sm6115_reset_desc,
+     }, {
+             .compatible = "qcom,sm6115-lpasscc",
+             .data = &lpasscc_sm6115_reset_desc,
+     },
+     { },
+};
+MODULE_DEVICE_TABLE(of, lpasscc_sm6115_match_table);

Everything here is almost the same as sc8280xp one, so this should be
added to sc8280xp. You cut some boilerplate and additional driver.

We have been there. It quickly becomes a nightmare to maintain.
Consider dispcc-sm8250.c

But I agree with you, this code looks too similar. If we expect more
similar lpasscc drivers, which provide no clocks, just several resets,
maybe we can create a common generic wrapper and make resets lists
corresponding driver data?

-- 
With best wishes
Dmitry

On 26/08/2023 16:09, Dmitry Baryshkov wrote:

quoted

quoted

+MODULE_DEVICE_TABLE(of, lpasscc_sm6115_match_table);

Everything here is almost the same as sc8280xp one, so this should be
added to sc8280xp. You cut some boilerplate and additional driver.

We have been there. It quickly becomes a nightmare to maintain.
Consider dispcc-sm8250.c

Because too much was added. I do not propose to keep all resets here.

But I agree with you, this code looks too similar. If we expect more
similar lpasscc drivers, which provide no clocks, just several resets,
maybe we can create a common generic wrapper and make resets lists
corresponding driver data?

This would also work.

Best regards,
Krzysztof

On 26.08.2023 16:29, Krzysztof Kozlowski wrote:

On 26/08/2023 16:09, Dmitry Baryshkov wrote:

quoted

quoted

quoted

+MODULE_DEVICE_TABLE(of, lpasscc_sm6115_match_table);

Everything here is almost the same as sc8280xp one, so this should be
added to sc8280xp. You cut some boilerplate and additional driver.

We have been there. It quickly becomes a nightmare to maintain.
Consider dispcc-sm8250.c

Because too much was added. I do not propose to keep all resets here.

quoted

But I agree with you, this code looks too similar. If we expect more
similar lpasscc drivers, which provide no clocks, just several resets,
maybe we can create a common generic wrapper and make resets lists
corresponding driver data?

This would also work.

Sounds like a good idea until somebody at qualcomm decides to add
support for bypassing adsp that only works on chromebooks that may get
cancelled or super secret internal devboards and the driver will gain
support for clocks..

But I guess that person will have to worry about squaring this out.

Konrad