From: Johan Hovold <johan+linaro@kernel.org> Date: 2022-07-13 13:18:29
This series adds the missing devicetree binding for SC8280XP, clean up
the current bindings somewhat and fixes a related driver warning when an
optional wakeup interrupt is missing.
The last four patches fix up the SC8280XP devicetree that's currently in
Bjorn's tree and addresses some DT schema warnings in other Qualcomm
devicetrees and are only included here for completeness.
The binding and driver updates are expected to go though the USB tree,
while the devicetree updates can be picked up by Bjorn once the binding
updates have been merged.
Johan
Johan Hovold (7):
dt-bindings: usb: qcom,dwc3: add SC8280XP binding
dt-bindings: usb: qcom,dwc3: refine interrupt requirements
usb: dwc3: qcom: fix missing optional irq warnings
arm64: dts: qcom: sc8280xp: fix USB clock order
arm64: dts: qcom: sc8280xp: fix USB interrupts
arm64: dts: qcom: sc7280: reorder USB interrupts
arm64: dts: qcom: reorder USB interrupts
.../devicetree/bindings/usb/qcom,dwc3.yaml | 152 ++++++++++++++++--
arch/arm/boot/dts/qcom-sdx65.dtsi | 10 +-
arch/arm64/boot/dts/qcom/sc7280.dtsi | 15 +-
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 28 ++--
arch/arm64/boot/dts/qcom/sm8250.dtsi | 20 ++-
arch/arm64/boot/dts/qcom/sm8350.dtsi | 20 ++-
drivers/usb/dwc3/dwc3-qcom.c | 4 +-
7 files changed, 194 insertions(+), 55 deletions(-)
--
2.35.1
From: Johan Hovold <johan+linaro@kernel.org> Date: 2022-07-13 13:18:05
Not all platforms have all of the four currently supported wakeup
interrupts so use the optional irq helpers when looking up interrupts to
avoid printing error messages when an optional interrupt is not found:
dwc3-qcom a6f8800.usb: error -ENXIO: IRQ hs_phy_irq not found
Fixes: a4333c3a6ba9 ("usb: dwc3: Add Qualcomm DWC3 glue driver")
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
---
drivers/usb/dwc3/dwc3-qcom.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
From: Andrew Halaney <hidden> Date: 2022-07-13 14:00:16
On Wed, Jul 13, 2022 at 03:13:36PM +0200, Johan Hovold wrote:
quoted hunk
Not all platforms have all of the four currently supported wakeup
interrupts so use the optional irq helpers when looking up interrupts to
avoid printing error messages when an optional interrupt is not found:
dwc3-qcom a6f8800.usb: error -ENXIO: IRQ hs_phy_irq not found
Fixes: a4333c3a6ba9 ("usb: dwc3: Add Qualcomm DWC3 glue driver")
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
---
drivers/usb/dwc3/dwc3-qcom.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
From: Johan Hovold <johan+linaro@kernel.org> Date: 2022-07-13 13:18:08
Not all platforms have all of the four wakeup interrupts currently
described by the bindings.
Specifically, MSM8953/6/8 and SDM660 do not use the DP/DM interrupts,
while the SS PHY interrupt is optional on SDM660 and SC7280.
Note that no devicetree in mainline specify any wakeup interrupts for
- qcom,ipq4019-dwc3
- qcom,ipq6018-dwc3
- qcom,ipq8064-dwc3
- qcom,ipq8074-dwc3
- qcom,msm8994-dwc3
- qcom,qcs404-dwc3
but let's keep the schema warnings about that for now.
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
---
.../devicetree/bindings/usb/qcom,dwc3.yaml | 60 +++++++++++++++++--
1 file changed, 55 insertions(+), 5 deletions(-)
From: Krzysztof Kozlowski <hidden> Date: 2022-07-14 10:50:42
On 13/07/2022 15:13, Johan Hovold wrote:
quoted hunk
Not all platforms have all of the four wakeup interrupts currently
described by the bindings.
Specifically, MSM8953/6/8 and SDM660 do not use the DP/DM interrupts,
while the SS PHY interrupt is optional on SDM660 and SC7280.
Note that no devicetree in mainline specify any wakeup interrupts for
- qcom,ipq4019-dwc3
- qcom,ipq6018-dwc3
- qcom,ipq8064-dwc3
- qcom,ipq8074-dwc3
- qcom,msm8994-dwc3
- qcom,qcs404-dwc3
but let's keep the schema warnings about that for now.
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
---
.../devicetree/bindings/usb/qcom,dwc3.yaml | 60 +++++++++++++++++--
1 file changed, 55 insertions(+), 5 deletions(-)
From: Johan Hovold <johan+linaro@kernel.org> Date: 2022-07-13 13:18:12
Add SC8280XP to the DT schema.
Note that the SC8280XP controllers use the common set of five clocks and
an additional set of four interconnect clocks whose purpose is not
entirely clear at this point.
The set of wakeup interrupts is also different for SC8280XP.
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
---
.../devicetree/bindings/usb/qcom,dwc3.yaml | 102 +++++++++++++++---
1 file changed, 88 insertions(+), 14 deletions(-)
@@ -66,11 +67,11 @@ properties:-mock_utmi::Mock utmi clock needed for ITP/SOF generation in hostmode. Its frequency should be 19.2MHz.minItems:1-maxItems:6+maxItems:9clock-names:minItems:1-maxItems:6+maxItems:9assigned-clocks:items:
@@ -93,20 +94,10 @@ properties:-const:apps-usbinterrupts:-items:--description:The interrupt that is asserted-when a wakeup event is received on USB2 bus.--description:The interrupt that is asserted-when a wakeup event is received on USB3 bus.--description:Wakeup event on DM line.--description:Wakeup event on DP line.+maxItems:4interrupt-names:-items:--const:hs_phy_irq--const:ss_phy_irq--const:dm_hs_phy_irq--const:dp_hs_phy_irq+maxItems:4qcom,select-utmi-as-pipe-clk:description:
@@ -311,6 +324,67 @@ allOf:-const:mock_utmi-const:xo+-if:+properties:+compatible:+contains:+enum:+-qcom,ipq4019-dwc3+-qcom,ipq6018-dwc3+-qcom,ipq8064-dwc3+-qcom,ipq8074-dwc3+-qcom,msm8953-dwc3+-qcom,msm8994-dwc3+-qcom,msm8996-dwc3+-qcom,msm8998-dwc3+-qcom,qcs404-dwc3+-qcom,sc7180-dwc3+-qcom,sc7280-dwc3+-qcom,sdm660-dwc3+-qcom,sdm845-dwc3+-qcom,sdx55-dwc3+-qcom,sdx65-dwc3+-qcom,sm4250-dwc3+-qcom,sm6115-dwc3+-qcom,sm6125-dwc3+-qcom,sm6350-dwc3+-qcom,sm8150-dwc3+-qcom,sm8250-dwc3+-qcom,sm8350-dwc3+-qcom,sm8450-dwc3+then:+properties:+interrupts:+items:+-description:The interrupt that is asserted+when a wakeup event is received on USB2 bus.+-description:The interrupt that is asserted+when a wakeup event is received on USB3 bus.+-description:Wakeup event on DM line.+-description:Wakeup event on DP line.+interrupt-names:+items:+-const:hs_phy_irq+-const:ss_phy_irq+-const:dm_hs_phy_irq+-const:dp_hs_phy_irq++-if:+properties:+compatible:+contains:+enum:+-qcom,sc8280xp-dwc3+then:+properties:+interrupts:+maxItems:4+interrupt-names:+items:+-const:pwr_event+-const:dp_hs_phy_irq+-const:dm_hs_phy_irq+-const:ss_phy_irqadditionalProperties:false
From: Krzysztof Kozlowski <hidden> Date: 2022-07-14 10:48:49
On 13/07/2022 15:13, Johan Hovold wrote:
Add SC8280XP to the DT schema.
Note that the SC8280XP controllers use the common set of five clocks and
an additional set of four interconnect clocks whose purpose is not
entirely clear at this point.
Thank you for your patch. There is something to discuss/improve.
From: Krzysztof Kozlowski <hidden> Date: 2022-07-14 10:51:28
On 13/07/2022 15:13, Johan Hovold wrote:
Add SC8280XP to the DT schema.
Note that the SC8280XP controllers use the common set of five clocks and
an additional set of four interconnect clocks whose purpose is not
entirely clear at this point.
The set of wakeup interrupts is also different for SC8280XP.
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
---
Second patch answers my questions, so:
Reviewed-by: Krzysztof Kozlowski <redacted>
Best regards,
Krzysztof
From: Johan Hovold <johan+linaro@kernel.org> Date: 2022-07-13 13:18:16
Three SoCs did not follow the interrupt order specified by the USB
controller binding.
While keeping the non-SuperSpeed interrupts together seems natural,
reorder the interrupts to match the binding.
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
---
arch/arm/boot/dts/qcom-sdx65.dtsi | 10 ++++++----
arch/arm64/boot/dts/qcom/sm8250.dtsi | 20 ++++++++++++--------
arch/arm64/boot/dts/qcom/sm8350.dtsi | 20 ++++++++++++--------
3 files changed, 30 insertions(+), 20 deletions(-)
From: Krzysztof Kozlowski <hidden> Date: 2022-07-14 10:54:30
On 13/07/2022 15:13, Johan Hovold wrote:
Three SoCs did not follow the interrupt order specified by the USB
controller binding.
While keeping the non-SuperSpeed interrupts together seems natural,
reorder the interrupts to match the binding.
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Acked-by: Krzysztof Kozlowski <redacted>
Best regards,
Krzysztof
From: Johan Hovold <johan+linaro@kernel.org> Date: 2022-07-13 13:18:19
The two single-port SC8280XP USB controllers do not have an hs_phy_irq
interrupt. Instead they have a pwr_event interrupt which is distinct
from the former and not yet supported by the driver.
Fix the USB node interrupt names so that they match the devicetree
binding.
Fixes: 152d1faf1e2f ("arm64: dts: qcom: add SC8280XP platform")
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
---
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
From: Andrew Halaney <hidden> Date: 2022-07-13 14:12:39
On Wed, Jul 13, 2022 at 03:13:38PM +0200, Johan Hovold wrote:
quoted hunk
The two single-port SC8280XP USB controllers do not have an hs_phy_irq
interrupt. Instead they have a pwr_event interrupt which is distinct
from the former and not yet supported by the driver.
Fix the USB node interrupt names so that they match the devicetree
binding.
Fixes: 152d1faf1e2f ("arm64: dts: qcom: add SC8280XP platform")
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
---
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
For this specific change to pwr_event:
Reviewed-by: Andrew Halaney [off-list ref]
That being said, I was reviewing this against the (fairly old)
downstream release I have, and the IRQs defined there look like this:
interrupts-extended = <&pdc 12 IRQ_TYPE_EDGE_RISING>,
<&intc GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 136 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 13 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "dp_hs_phy_irq", "pwr_event_irq",
"ss_phy_irq", "dm_hs_phy_irq";
The part I want to highlight is that the "pwr_event" irq downstream maps
to <&intc GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>, but the current upstream
devicetree I'm looking at has it mapped to <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>
Do you happen to have any source you can also check to confirm if this
is a bug or not?
Thanks,
Andrew
From: Johan Hovold <johan@kernel.org> Date: 2022-07-13 14:35:27
On Wed, Jul 13, 2022 at 09:12:28AM -0500, Andrew Halaney wrote:
On Wed, Jul 13, 2022 at 03:13:38PM +0200, Johan Hovold wrote:
quoted
The two single-port SC8280XP USB controllers do not have an hs_phy_irq
interrupt. Instead they have a pwr_event interrupt which is distinct
from the former and not yet supported by the driver.
Fix the USB node interrupt names so that they match the devicetree
binding.
Fixes: 152d1faf1e2f ("arm64: dts: qcom: add SC8280XP platform")
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
---
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
For this specific change to pwr_event:
Reviewed-by: Andrew Halaney [off-list ref]
That being said, I was reviewing this against the (fairly old)
downstream release I have, and the IRQs defined there look like this:
interrupts-extended = <&pdc 12 IRQ_TYPE_EDGE_RISING>,
<&intc GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 136 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 13 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "dp_hs_phy_irq", "pwr_event_irq",
"ss_phy_irq", "dm_hs_phy_irq";
The part I want to highlight is that the "pwr_event" irq downstream maps
to <&intc GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>, but the current upstream
devicetree I'm looking at has it mapped to <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>
Do you happen to have any source you can also check to confirm if this
is a bug or not?
Good catch! I believe this is another copy-paste error when creating
base dtsi based on some vendor source (or perhaps an error carried over
from an earlier version).
The vendor devicetree I have access to also has 811 here, which matches
the pattern for usb_0 (dwc3 interrupt + 1).
Do you mind if I fold a fix for that into a v2 of this patch?
Thanks for reviewing!
Johan
From: Andrew Halaney <hidden> Date: 2022-07-13 14:43:31
On Wed, Jul 13, 2022 at 04:35:22PM +0200, Johan Hovold wrote:
On Wed, Jul 13, 2022 at 09:12:28AM -0500, Andrew Halaney wrote:
quoted
On Wed, Jul 13, 2022 at 03:13:38PM +0200, Johan Hovold wrote:
quoted
The two single-port SC8280XP USB controllers do not have an hs_phy_irq
interrupt. Instead they have a pwr_event interrupt which is distinct
from the former and not yet supported by the driver.
Fix the USB node interrupt names so that they match the devicetree
binding.
Fixes: 152d1faf1e2f ("arm64: dts: qcom: add SC8280XP platform")
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
---
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
For this specific change to pwr_event:
Reviewed-by: Andrew Halaney [off-list ref]
That being said, I was reviewing this against the (fairly old)
downstream release I have, and the IRQs defined there look like this:
interrupts-extended = <&pdc 12 IRQ_TYPE_EDGE_RISING>,
<&intc GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 136 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 13 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "dp_hs_phy_irq", "pwr_event_irq",
"ss_phy_irq", "dm_hs_phy_irq";
The part I want to highlight is that the "pwr_event" irq downstream maps
to <&intc GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>, but the current upstream
devicetree I'm looking at has it mapped to <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>
Do you happen to have any source you can also check to confirm if this
is a bug or not?
Good catch! I believe this is another copy-paste error when creating
base dtsi based on some vendor source (or perhaps an error carried over
from an earlier version).
The vendor devicetree I have access to also has 811 here, which matches
the pattern for usb_0 (dwc3 interrupt + 1).
Do you mind if I fold a fix for that into a v2 of this patch?
Thanks for reviewing!
Sounds good, feel free to add my R-B with that change as well!
From: Krzysztof Kozlowski <hidden> Date: 2022-07-14 10:53:02
On 13/07/2022 15:13, Johan Hovold wrote:
The two single-port SC8280XP USB controllers do not have an hs_phy_irq
interrupt. Instead they have a pwr_event interrupt which is distinct
from the former and not yet supported by the driver.
Fix the USB node interrupt names so that they match the devicetree
binding.
Fixes: 152d1faf1e2f ("arm64: dts: qcom: add SC8280XP platform")
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
---
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
Acked-by: Krzysztof Kozlowski <redacted>
Best regards,
Krzysztof
From: Johan Hovold <johan+linaro@kernel.org> Date: 2022-07-13 13:18:22
Only one of the USB controllers supports SuperSpeed and have an SS PHY
wakeup interrupt.
Reorder the interrupts so that they match the updated binding which
specifically has the optional interrupt last.
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 15 ++++++++-------
1 file changed, 8 insertions(+), 7 deletions(-)
From: Krzysztof Kozlowski <hidden> Date: 2022-07-14 10:54:17
On 13/07/2022 15:13, Johan Hovold wrote:
Only one of the USB controllers supports SuperSpeed and have an SS PHY
wakeup interrupt.
Reorder the interrupts so that they match the updated binding which
specifically has the optional interrupt last.
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Acked-by: Krzysztof Kozlowski <redacted>
Best regards,
Krzysztof
From: Johan Hovold <johan+linaro@kernel.org> Date: 2022-07-13 13:18:26
Fix the USB controller clock order and naming so that they match the
devicetree binding.
Note that the driver currently simply enables all clocks in the order
that they are specified in the devicetree. Reordering the clocks as per
the binding means that the only explicit ordering constraint found in
the vendor driver, that cfg_noc should be enabled before the core_clk,
is now honoured.
Fixes: 152d1faf1e2f ("arm64: dts: qcom: add SC8280XP platform")
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
---
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
From: Krzysztof Kozlowski <hidden> Date: 2022-07-14 10:52:31
On 13/07/2022 15:13, Johan Hovold wrote:
quoted hunk
Fix the USB controller clock order and naming so that they match the
devicetree binding.
Note that the driver currently simply enables all clocks in the order
that they are specified in the devicetree. Reordering the clocks as per
the binding means that the only explicit ordering constraint found in
the vendor driver, that cfg_noc should be enabled before the core_clk,
is now honoured.
Fixes: 152d1faf1e2f ("arm64: dts: qcom: add SC8280XP platform")
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
---
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)