@@ -24,9 +24,13 @@ select:properties:compatible:-items:--const:arm,pl011--const:arm,primecell+oneOf:+-items:+-const:arm,pl011+-const:arm,primecell+-items:+-const:arm,pl011+-const:arm,xlnx-uart# xilinx uart as platform device
'arm,primecell' means the block has ID registers. Are you saying
this implementation doesn't?
The ID registers do not have any Xilinx specific identifiers.
However there are differences like 32-bit access.
Hope that the current approach is fine with you.
Could you please guide how to go about it.
No, I don't know what the differences are in your h/w. You have ID
registers, but changed the IP and didn't change the ID registers? How
has the IP changed?
Rob
No, I don't know what the differences are in your h/w. You have ID
registers, but changed the IP and didn't change the ID registers? How
has the IP changed?
The IP is not changed and the ID registers are not updated.
The limitation is coming from the AXI port that the IP is connected to.
The axi port is allowing only the 32 bit access.
The same information will be updated in the Versal TRM.
From: Michal Simek <hidden> Date: 2022-07-14 10:55:34
Hi Rob and Krzysztof,
On 6/14/22 14:21, Shubhrajyoti Datta wrote:
quoted
quoted
<snip>
quoted
No, I don't know what the differences are in your h/w. You have ID
registers, but changed the IP and didn't change the ID registers? How
has the IP changed?
The IP is not changed and the ID registers are not updated.
The limitation is coming from the AXI port that the IP is connected to.
The axi port is allowing only the 32 bit access.
The same information will be updated in the Versal TRM.
Can you please give us your recommendation how to process with this?
Thanks,
Michal
From: Krzysztof Kozlowski <hidden> Date: 2022-07-14 11:59:18
On 14/07/2022 12:55, Michal Simek wrote:
Hi Rob and Krzysztof,
On 6/14/22 14:21, Shubhrajyoti Datta wrote:
quoted
quoted
quoted
<snip>
quoted
No, I don't know what the differences are in your h/w. You have ID
registers, but changed the IP and didn't change the ID registers? How
has the IP changed?
The IP is not changed and the ID registers are not updated.
The limitation is coming from the AXI port that the IP is connected to.
The axi port is allowing only the 32 bit access.
The same information will be updated in the Versal TRM.
Can you please give us your recommendation how to process with this?
Unfortunately I don't think that anyone remembers context from last
year, especially me who was not Cced. Rob responded at end of March and
it took two months to get back any answer. Such slow response time from
submitter does not help to stay in the context. :(
Best regards,
Krzysztof
-----Original Message-----
From: Krzysztof Kozlowski <redacted>
Sent: Thursday, July 14, 2022 5:29 PM
To: Michal Simek <redacted>; Shubhrajyoti Datta
[off-list ref]; Rob Herring [off-list ref]; Krzysztof
Kozlowski [off-list ref]
Cc: Shubhrajyoti Datta <redacted>; linux-serial@vger.kernel.org;
devicetree@vger.kernel.org; gregkh@linuxfoundation.org; Srinivas Goud
[off-list ref]
Subject: Re: [PATCH 1/2] dt-bindings: serial: pl011: Add 'arm,xlnx-uart'
CAUTION: This message has originated from an External Source. Please use
proper judgment and caution when opening attachments, clicking links, or
responding to this email.
On 14/07/2022 12:55, Michal Simek wrote:
quoted
Hi Rob and Krzysztof,
On 6/14/22 14:21, Shubhrajyoti Datta wrote:
quoted
quoted
quoted
<snip>
quoted
No, I don't know what the differences are in your h/w. You have ID
registers, but changed the IP and didn't change the ID registers?
How has the IP changed?
The IP is not changed and the ID registers are not updated.
The limitation is coming from the AXI port that the IP is connected to.
The axi port is allowing only the 32 bit access.
The same information will be updated in the Versal TRM.
Can you please give us your recommendation how to process with this?
Unfortunately I don't think that anyone remembers context from last year,
especially me who was not Cced. Rob responded at end of March and it took
two months to get back any answer. Such slow response time from submitter
does not help to stay in the context. :(
I had to contact the hardware team and get the details on the issue it took me sometime to get a response.
I will summarize
We are using the ip from ARM but the AXI port that we hooked has a limitation that it allows only 32 bit accesses.
So to tide over the and differentiate I am adding a new compatible arm,xlnx-uart.
From: Michal Simek <michal.simek@amd.com> Date: 2022-07-20 13:42:08
On 7/14/22 14:14, Datta, Shubhrajyoti wrote:
[AMD Official Use Only - General]
quoted
-----Original Message-----
From: Krzysztof Kozlowski <redacted>
Sent: Thursday, July 14, 2022 5:29 PM
To: Michal Simek <redacted>; Shubhrajyoti Datta
[off-list ref]; Rob Herring [off-list ref]; Krzysztof
Kozlowski [off-list ref]
Cc: Shubhrajyoti Datta <redacted>; linux-serial@vger.kernel.org;
devicetree@vger.kernel.org; gregkh@linuxfoundation.org; Srinivas Goud
[off-list ref]
Subject: Re: [PATCH 1/2] dt-bindings: serial: pl011: Add 'arm,xlnx-uart'
CAUTION: This message has originated from an External Source. Please use
proper judgment and caution when opening attachments, clicking links, or
responding to this email.
On 14/07/2022 12:55, Michal Simek wrote:
quoted
Hi Rob and Krzysztof,
On 6/14/22 14:21, Shubhrajyoti Datta wrote:
quoted
quoted
quoted
<snip>
quoted
No, I don't know what the differences are in your h/w. You have ID
registers, but changed the IP and didn't change the ID registers?
How has the IP changed?
The IP is not changed and the ID registers are not updated.
The limitation is coming from the AXI port that the IP is connected to.
The axi port is allowing only the 32 bit access.
The same information will be updated in the Versal TRM.
Can you please give us your recommendation how to process with this?
Unfortunately I don't think that anyone remembers context from last year,
especially me who was not Cced. Rob responded at end of March and it took
two months to get back any answer. Such slow response time from submitter
does not help to stay in the context. :(
I had to contact the hardware team and get the details on the issue it took me sometime to get a response.
I will summarize
We are using the ip from ARM but the AXI port that we hooked has a limitation that it allows only 32 bit accesses.
So to tide over the and differentiate I am adding a new compatible arm,xlnx-uart.
ok.
Shubhrajyoti: Please send this series again with updated commit message in 1/2
which contains information you provided here. That means it will be v2 version.
Thanks,
Michal
From: Raviteja Narayanam <redacted>
The xilinx uart used in Versal SOC follows arm pl011 implementation
with just a minor change in data bus width. The minimum data
transaction width in Versal SOC is 32-bit as specified in the
TRM (Chapter 39: Transaction attributes). Pl011 defaults to 16-bit
in the driver.
So, add the xilinx uart as platform device with properties specified
in 'vendor_data' structure.
Signed-off-by: Raviteja Narayanam <redacted>
Signed-off-by: Shubhrajyoti Datta <redacted>
---
drivers/tty/serial/amba-pl011.c | 33 +++++++++++++++++++++++++++++++--
1 file changed, 31 insertions(+), 2 deletions(-)