[PATCH] arm64: dts: lx2160a: correct cache-sets info
From: Peng Fan (OSS) <hidden>
Date: 2021-11-12 06:30:33
Also in:
linux-arm-kernel, lkml
Subsystem:
arm/freescale layerscape arm architecture, the rest · Maintainers:
Frank Li, Linus Torvalds
From: Peng Fan <peng.fan@nxp.com>
A72 Cluster has 48KB Icache, 32KB Dcache and 1MB L2 Cache
- ICache is 3-way set-associative
- Dcache is 2-way set-associative
- Line size are 64bytes
So correct the cache-sets info.
Fixes: d548c217c6a3c ("arm64: dts: add QorIQ LX2160A SoC support")
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
V1:
I am not sure whether this is intentional or not using the original cache
sets value. If the original value is correct, please drop this patch.
.../arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 64 +++++++++----------
1 file changed, 32 insertions(+), 32 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
index dc8661ebd1f6..e1a10bc4c5a9 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi@@ -34,10 +34,10 @@ cpu0: cpu@0 { clocks = <&clockgen QORIQ_CLK_CMUX 0>; d-cache-size = <0x8000>; d-cache-line-size = <64>; - d-cache-sets = <128>; + d-cache-sets = <256>; i-cache-size = <0xC000>; i-cache-line-size = <64>; - i-cache-sets = <192>; + i-cache-sets = <256>; next-level-cache = <&cluster0_l2>; cpu-idle-states = <&cpu_pw15>; #cooling-cells = <2>;
@@ -51,10 +51,10 @@ cpu1: cpu@1 { clocks = <&clockgen QORIQ_CLK_CMUX 0>; d-cache-size = <0x8000>; d-cache-line-size = <64>; - d-cache-sets = <128>; + d-cache-sets = <256>; i-cache-size = <0xC000>; i-cache-line-size = <64>; - i-cache-sets = <192>; + i-cache-sets = <256>; next-level-cache = <&cluster0_l2>; cpu-idle-states = <&cpu_pw15>; #cooling-cells = <2>;
@@ -68,10 +68,10 @@ cpu100: cpu@100 { clocks = <&clockgen QORIQ_CLK_CMUX 1>; d-cache-size = <0x8000>; d-cache-line-size = <64>; - d-cache-sets = <128>; + d-cache-sets = <256>; i-cache-size = <0xC000>; i-cache-line-size = <64>; - i-cache-sets = <192>; + i-cache-sets = <256>; next-level-cache = <&cluster1_l2>; cpu-idle-states = <&cpu_pw15>; #cooling-cells = <2>;
@@ -85,10 +85,10 @@ cpu101: cpu@101 { clocks = <&clockgen QORIQ_CLK_CMUX 1>; d-cache-size = <0x8000>; d-cache-line-size = <64>; - d-cache-sets = <128>; + d-cache-sets = <256>; i-cache-size = <0xC000>; i-cache-line-size = <64>; - i-cache-sets = <192>; + i-cache-sets = <256>; next-level-cache = <&cluster1_l2>; cpu-idle-states = <&cpu_pw15>; #cooling-cells = <2>;
@@ -102,10 +102,10 @@ cpu200: cpu@200 { clocks = <&clockgen QORIQ_CLK_CMUX 2>; d-cache-size = <0x8000>; d-cache-line-size = <64>; - d-cache-sets = <128>; + d-cache-sets = <256>; i-cache-size = <0xC000>; i-cache-line-size = <64>; - i-cache-sets = <192>; + i-cache-sets = <256>; next-level-cache = <&cluster2_l2>; cpu-idle-states = <&cpu_pw15>; #cooling-cells = <2>;
@@ -119,10 +119,10 @@ cpu201: cpu@201 { clocks = <&clockgen QORIQ_CLK_CMUX 2>; d-cache-size = <0x8000>; d-cache-line-size = <64>; - d-cache-sets = <128>; + d-cache-sets = <256>; i-cache-size = <0xC000>; i-cache-line-size = <64>; - i-cache-sets = <192>; + i-cache-sets = <256>; next-level-cache = <&cluster2_l2>; cpu-idle-states = <&cpu_pw15>; #cooling-cells = <2>;
@@ -136,10 +136,10 @@ cpu300: cpu@300 { clocks = <&clockgen QORIQ_CLK_CMUX 3>; d-cache-size = <0x8000>; d-cache-line-size = <64>; - d-cache-sets = <128>; + d-cache-sets = <256>; i-cache-size = <0xC000>; i-cache-line-size = <64>; - i-cache-sets = <192>; + i-cache-sets = <256>; next-level-cache = <&cluster3_l2>; cpu-idle-states = <&cpu_pw15>; #cooling-cells = <2>;
@@ -153,10 +153,10 @@ cpu301: cpu@301 { clocks = <&clockgen QORIQ_CLK_CMUX 3>; d-cache-size = <0x8000>; d-cache-line-size = <64>; - d-cache-sets = <128>; + d-cache-sets = <256>; i-cache-size = <0xC000>; i-cache-line-size = <64>; - i-cache-sets = <192>; + i-cache-sets = <256>; next-level-cache = <&cluster3_l2>; cpu-idle-states = <&cpu_pw15>; #cooling-cells = <2>;
@@ -170,10 +170,10 @@ cpu400: cpu@400 { clocks = <&clockgen QORIQ_CLK_CMUX 4>; d-cache-size = <0x8000>; d-cache-line-size = <64>; - d-cache-sets = <128>; + d-cache-sets = <256>; i-cache-size = <0xC000>; i-cache-line-size = <64>; - i-cache-sets = <192>; + i-cache-sets = <256>; next-level-cache = <&cluster4_l2>; cpu-idle-states = <&cpu_pw15>; #cooling-cells = <2>;
@@ -187,10 +187,10 @@ cpu401: cpu@401 { clocks = <&clockgen QORIQ_CLK_CMUX 4>; d-cache-size = <0x8000>; d-cache-line-size = <64>; - d-cache-sets = <128>; + d-cache-sets = <256>; i-cache-size = <0xC000>; i-cache-line-size = <64>; - i-cache-sets = <192>; + i-cache-sets = <256>; next-level-cache = <&cluster4_l2>; cpu-idle-states = <&cpu_pw15>; #cooling-cells = <2>;
@@ -204,10 +204,10 @@ cpu500: cpu@500 { clocks = <&clockgen QORIQ_CLK_CMUX 5>; d-cache-size = <0x8000>; d-cache-line-size = <64>; - d-cache-sets = <128>; + d-cache-sets = <256>; i-cache-size = <0xC000>; i-cache-line-size = <64>; - i-cache-sets = <192>; + i-cache-sets = <256>; next-level-cache = <&cluster5_l2>; cpu-idle-states = <&cpu_pw15>; #cooling-cells = <2>;
@@ -221,10 +221,10 @@ cpu501: cpu@501 { clocks = <&clockgen QORIQ_CLK_CMUX 5>; d-cache-size = <0x8000>; d-cache-line-size = <64>; - d-cache-sets = <128>; + d-cache-sets = <256>; i-cache-size = <0xC000>; i-cache-line-size = <64>; - i-cache-sets = <192>; + i-cache-sets = <256>; next-level-cache = <&cluster5_l2>; cpu-idle-states = <&cpu_pw15>; #cooling-cells = <2>;
@@ -238,10 +238,10 @@ cpu600: cpu@600 { clocks = <&clockgen QORIQ_CLK_CMUX 6>; d-cache-size = <0x8000>; d-cache-line-size = <64>; - d-cache-sets = <128>; + d-cache-sets = <256>; i-cache-size = <0xC000>; i-cache-line-size = <64>; - i-cache-sets = <192>; + i-cache-sets = <256>; next-level-cache = <&cluster6_l2>; cpu-idle-states = <&cpu_pw15>; #cooling-cells = <2>;
@@ -255,10 +255,10 @@ cpu601: cpu@601 { clocks = <&clockgen QORIQ_CLK_CMUX 6>; d-cache-size = <0x8000>; d-cache-line-size = <64>; - d-cache-sets = <128>; + d-cache-sets = <256>; i-cache-size = <0xC000>; i-cache-line-size = <64>; - i-cache-sets = <192>; + i-cache-sets = <256>; next-level-cache = <&cluster6_l2>; cpu-idle-states = <&cpu_pw15>; #cooling-cells = <2>;
@@ -272,10 +272,10 @@ cpu700: cpu@700 { clocks = <&clockgen QORIQ_CLK_CMUX 7>; d-cache-size = <0x8000>; d-cache-line-size = <64>; - d-cache-sets = <128>; + d-cache-sets = <256>; i-cache-size = <0xC000>; i-cache-line-size = <64>; - i-cache-sets = <192>; + i-cache-sets = <256>; next-level-cache = <&cluster7_l2>; cpu-idle-states = <&cpu_pw15>; #cooling-cells = <2>;
@@ -289,10 +289,10 @@ cpu701: cpu@701 { clocks = <&clockgen QORIQ_CLK_CMUX 7>; d-cache-size = <0x8000>; d-cache-line-size = <64>; - d-cache-sets = <128>; + d-cache-sets = <256>; i-cache-size = <0xC000>; i-cache-line-size = <64>; - i-cache-sets = <192>; + i-cache-sets = <256>; next-level-cache = <&cluster7_l2>; cpu-idle-states = <&cpu_pw15>; #cooling-cells = <2>;
--
2.25.1