[PATCH 0/7] arm64: dts: ls1028: GPU support and cleanups

STALE1731d

15 messages, 4 authors, 2022-01-20 · open the first message on its own page

[PATCH 0/7] arm64: dts: ls1028: GPU support and cleanups

From: Michael Walle <hidden>
Date: 2021-08-31 13:40:26

In an attempt to unify u-boot's and linux' device tree for the LS1028A SoC
we first need to clean up some network related stuff. Vladimir suggested to
move the Ethernet PHYs into the MDIO controller node, which is already the
case for u-boot's device tree. Further we unify the use of phy-mode and
phy-connection-type. Both have the same meaning, but phy-mode is used more
often in the kernel and for the ls1028a both were used. Replace
phy-connection-type with phy-mode.

Further move all the nodes which belongs to the CCSR into the /soc node.
These are the Mali display conntroller and its associated pixel clock PLL.
Finally, add the GPU node for the etnaviv driver under /soc.

Michael Walle (7):
  arm64: dts: ls1028a: move pixel clock pll into /soc
  arm64: dts: ls1028a: move Mali DP500 node into /soc
  arm64: dts: ls1028a: add Vivante GPU node
  arm64: dts: freescale: fix arm,sp805 compatible string
  arm64: dts: ls1028a: disable usb controller by default
  arm64: dts: ls1028a: move PHY nodes to MDIO controller
  arm64: dts: ls1028a: use phy-mode instead of phy-connection-type

 .../fsl-ls1028a-kontron-sl28-var1.dts         | 60 ++++++++--------
 .../fsl-ls1028a-kontron-sl28-var2.dts         | 17 ++---
 .../fsl-ls1028a-kontron-sl28-var4.dts         | 49 +++++++------
 .../freescale/fsl-ls1028a-kontron-sl28.dts    | 31 +++++----
 .../boot/dts/freescale/fsl-ls1028a-qds.dts    | 10 ++-
 .../boot/dts/freescale/fsl-ls1028a-rdb.dts    | 19 +++---
 .../arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 68 +++++++++++--------
 .../arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 16 ++---
 .../arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 16 ++---
 9 files changed, 149 insertions(+), 137 deletions(-)

-- 
2.30.2

[PATCH 1/7] arm64: dts: ls1028a: move pixel clock pll into /soc

From: Michael Walle <hidden>
Date: 2021-08-31 13:40:24

Move it inside the /soc subnode because it is part of the CCSR space.

Signed-off-by: Michael Walle <redacted>
---
 arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
index 343ecf0e8973..9a65a7118faa 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi

@@ -80,13 +80,6 @@ osc_27m: clock-osc-27m {
 		clock-output-names = "phy_27m";
 	};
 
-	dpclk: clock-controller@f1f0000 {
-		compatible = "fsl,ls1028a-plldig";
-		reg = <0x0 0xf1f0000 0x0 0xffff>;
-		#clock-cells = <0>;
-		clocks = <&osc_27m>;
-	};
-
 	firmware {
 		optee: optee  {
 			compatible = "linaro,optee-tz";

@@ -926,6 +919,13 @@ QORIQ_CLK_PLL_DIV(2)>,
 			status = "disabled";
 		};
 
+		dpclk: clock-controller@f1f0000 {
+			compatible = "fsl,ls1028a-plldig";
+			reg = <0x0 0xf1f0000 0x0 0x10000>;
+			#clock-cells = <0>;
+			clocks = <&osc_27m>;
+		};
+
 		tmu: tmu@1f80000 {
 			compatible = "fsl,qoriq-tmu";
 			reg = <0x0 0x1f80000 0x0 0x10000>;

-- 
2.30.2

[PATCH 2/7] arm64: dts: ls1028a: move Mali DP500 node into /soc

From: Michael Walle <hidden>
Date: 2021-08-31 13:40:29

Move it inside the /soc subnode because it is part of the CCSR space.

Signed-off-by: Michael Walle <redacted>
---
 .../arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 41 ++++++++++---------
 1 file changed, 21 insertions(+), 20 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
index 9a65a7118faa..92e4f004c1c2 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi

@@ -793,6 +793,27 @@ QORIQ_CLK_PLL_DIV(16)>,
 			clock-names = "wdog_clk", "apb_pclk";
 		};
 
+		malidp0: display@f080000 {
+			compatible = "arm,mali-dp500";
+			reg = <0x0 0xf080000 0x0 0x10000>;
+			interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>,
+				     <0 223 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "DE", "SE";
+			clocks = <&dpclk>,
+				 <&clockgen QORIQ_CLK_HWACCEL 2>,
+				 <&clockgen QORIQ_CLK_HWACCEL 2>,
+				 <&clockgen QORIQ_CLK_HWACCEL 2>;
+			clock-names = "pxlclk", "mclk", "aclk", "pclk";
+			arm,malidp-output-port-lines = /bits/ 8 <8 8 8>;
+			arm,malidp-arqos-value = <0xd000d000>;
+
+			port {
+				dpi0_out: endpoint {
+
+				};
+			};
+		};
+
 		sai1: audio-controller@f100000 {
 			#sound-dai-cells = <0>;
 			compatible = "fsl,vf610-sai";

@@ -1139,24 +1160,4 @@ ftm_alarm0: timer@2800000 {
 		};
 	};
 
-	malidp0: display@f080000 {
-		compatible = "arm,mali-dp500";
-		reg = <0x0 0xf080000 0x0 0x10000>;
-		interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 223 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-names = "DE", "SE";
-		clocks = <&dpclk>,
-			 <&clockgen QORIQ_CLK_HWACCEL 2>,
-			 <&clockgen QORIQ_CLK_HWACCEL 2>,
-			 <&clockgen QORIQ_CLK_HWACCEL 2>;
-		clock-names = "pxlclk", "mclk", "aclk", "pclk";
-		arm,malidp-output-port-lines = /bits/ 8 <8 8 8>;
-		arm,malidp-arqos-value = <0xd000d000>;
-
-		port {
-			dp0_out: endpoint {
-
-			};
-		};
-	};
 };

-- 
2.30.2

[PATCH 3/7] arm64: dts: ls1028a: add Vivante GPU node

From: Michael Walle <hidden>
Date: 2021-08-31 13:40:32

Recently, support for this particular Vivante GC7000 GPU was added to the
linux kernel. Add the corresponding device tree node.

Signed-off-by: Michael Walle <redacted>
---
 arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
index 92e4f004c1c2..876dea668a90 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi

@@ -814,6 +814,17 @@ dpi0_out: endpoint {
 			};
 		};
 
+		gpu: gpu@f0c0000 {
+			compatible = "vivante,gc";
+			reg = <0x0 0xf0c0000 0x0 0x10000>;
+			interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clockgen QORIQ_CLK_HWACCEL 2>,
+				 <&clockgen QORIQ_CLK_HWACCEL 2>,
+				 <&clockgen QORIQ_CLK_HWACCEL 2>;
+			clock-names = "core", "shader", "bus";
+			#cooling-cells = <2>;
+		};
+
 		sai1: audio-controller@f100000 {
 			#sound-dai-cells = <0>;
 			compatible = "fsl,vf610-sai";

-- 
2.30.2

[PATCH 4/7] arm64: dts: freescale: fix arm,sp805 compatible string

From: Michael Walle <hidden>
Date: 2021-08-31 13:40:34

According to Documentation/devicetree/bindings/watchdog/arm,sp805.yaml
the compatible is:
  compatible = "arm,sp805", "arm,primecell";

The current compatible string doesn't exist at all. Fix it.

Signed-off-by: Michael Walle <redacted>
---
 arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 16 ++++++++--------
 arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 16 ++++++++--------
 2 files changed, 16 insertions(+), 16 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
index f85e437f80b7..605072317243 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi

@@ -847,7 +847,7 @@ pcs7_3: ethernet-phy@3 {
 		};
 
 		cluster1_core0_watchdog: wdt@c000000 {
-			compatible = "arm,sp805-wdt", "arm,primecell";
+			compatible = "arm,sp805", "arm,primecell";
 			reg = <0x0 0xc000000 0x0 0x1000>;
 			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 					    QORIQ_CLK_PLL_DIV(16)>,

@@ -857,7 +857,7 @@ QORIQ_CLK_PLL_DIV(16)>,
 		};
 
 		cluster1_core1_watchdog: wdt@c010000 {
-			compatible = "arm,sp805-wdt", "arm,primecell";
+			compatible = "arm,sp805", "arm,primecell";
 			reg = <0x0 0xc010000 0x0 0x1000>;
 			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 					    QORIQ_CLK_PLL_DIV(16)>,

@@ -867,7 +867,7 @@ QORIQ_CLK_PLL_DIV(16)>,
 		};
 
 		cluster1_core2_watchdog: wdt@c020000 {
-			compatible = "arm,sp805-wdt", "arm,primecell";
+			compatible = "arm,sp805", "arm,primecell";
 			reg = <0x0 0xc020000 0x0 0x1000>;
 			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 					    QORIQ_CLK_PLL_DIV(16)>,

@@ -877,7 +877,7 @@ QORIQ_CLK_PLL_DIV(16)>,
 		};
 
 		cluster1_core3_watchdog: wdt@c030000 {
-			compatible = "arm,sp805-wdt", "arm,primecell";
+			compatible = "arm,sp805", "arm,primecell";
 			reg = <0x0 0xc030000 0x0 0x1000>;
 			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 					    QORIQ_CLK_PLL_DIV(16)>,

@@ -887,7 +887,7 @@ QORIQ_CLK_PLL_DIV(16)>,
 		};
 
 		cluster2_core0_watchdog: wdt@c100000 {
-			compatible = "arm,sp805-wdt", "arm,primecell";
+			compatible = "arm,sp805", "arm,primecell";
 			reg = <0x0 0xc100000 0x0 0x1000>;
 			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 					    QORIQ_CLK_PLL_DIV(16)>,

@@ -897,7 +897,7 @@ QORIQ_CLK_PLL_DIV(16)>,
 		};
 
 		cluster2_core1_watchdog: wdt@c110000 {
-			compatible = "arm,sp805-wdt", "arm,primecell";
+			compatible = "arm,sp805", "arm,primecell";
 			reg = <0x0 0xc110000 0x0 0x1000>;
 			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 					    QORIQ_CLK_PLL_DIV(16)>,

@@ -907,7 +907,7 @@ QORIQ_CLK_PLL_DIV(16)>,
 		};
 
 		cluster2_core2_watchdog: wdt@c120000 {
-			compatible = "arm,sp805-wdt", "arm,primecell";
+			compatible = "arm,sp805", "arm,primecell";
 			reg = <0x0 0xc120000 0x0 0x1000>;
 			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 					    QORIQ_CLK_PLL_DIV(16)>,

@@ -917,7 +917,7 @@ QORIQ_CLK_PLL_DIV(16)>,
 		};
 
 		cluster2_core3_watchdog: wdt@c130000 {
-			compatible = "arm,sp805-wdt", "arm,primecell";
+			compatible = "arm,sp805", "arm,primecell";
 			reg = <0x0 0xc130000 0x0 0x1000>;
 			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 					    QORIQ_CLK_PLL_DIV(16)>,

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
index 801ba9612d36..1282b61da8a5 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi

@@ -387,7 +387,7 @@ serial3: serial@21d0600 {
 		};
 
 		cluster1_core0_watchdog: wdt@c000000 {
-			compatible = "arm,sp805-wdt", "arm,primecell";
+			compatible = "arm,sp805", "arm,primecell";
 			reg = <0x0 0xc000000 0x0 0x1000>;
 			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 					    QORIQ_CLK_PLL_DIV(4)>,

@@ -397,7 +397,7 @@ QORIQ_CLK_PLL_DIV(4)>,
 		};
 
 		cluster1_core1_watchdog: wdt@c010000 {
-			compatible = "arm,sp805-wdt", "arm,primecell";
+			compatible = "arm,sp805", "arm,primecell";
 			reg = <0x0 0xc010000 0x0 0x1000>;
 			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 					    QORIQ_CLK_PLL_DIV(4)>,

@@ -407,7 +407,7 @@ QORIQ_CLK_PLL_DIV(4)>,
 		};
 
 		cluster2_core0_watchdog: wdt@c100000 {
-			compatible = "arm,sp805-wdt", "arm,primecell";
+			compatible = "arm,sp805", "arm,primecell";
 			reg = <0x0 0xc100000 0x0 0x1000>;
 			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 					    QORIQ_CLK_PLL_DIV(4)>,

@@ -417,7 +417,7 @@ QORIQ_CLK_PLL_DIV(4)>,
 		};
 
 		cluster2_core1_watchdog: wdt@c110000 {
-			compatible = "arm,sp805-wdt", "arm,primecell";
+			compatible = "arm,sp805", "arm,primecell";
 			reg = <0x0 0xc110000 0x0 0x1000>;
 			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 					    QORIQ_CLK_PLL_DIV(4)>,

@@ -427,7 +427,7 @@ QORIQ_CLK_PLL_DIV(4)>,
 		};
 
 		cluster3_core0_watchdog: wdt@c200000 {
-			compatible = "arm,sp805-wdt", "arm,primecell";
+			compatible = "arm,sp805", "arm,primecell";
 			reg = <0x0 0xc200000 0x0 0x1000>;
 			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 					    QORIQ_CLK_PLL_DIV(4)>,

@@ -437,7 +437,7 @@ QORIQ_CLK_PLL_DIV(4)>,
 		};
 
 		cluster3_core1_watchdog: wdt@c210000 {
-			compatible = "arm,sp805-wdt", "arm,primecell";
+			compatible = "arm,sp805", "arm,primecell";
 			reg = <0x0 0xc210000 0x0 0x1000>;
 			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 					    QORIQ_CLK_PLL_DIV(4)>,

@@ -447,7 +447,7 @@ QORIQ_CLK_PLL_DIV(4)>,
 		};
 
 		cluster4_core0_watchdog: wdt@c300000 {
-			compatible = "arm,sp805-wdt", "arm,primecell";
+			compatible = "arm,sp805", "arm,primecell";
 			reg = <0x0 0xc300000 0x0 0x1000>;
 			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 					    QORIQ_CLK_PLL_DIV(4)>,

@@ -457,7 +457,7 @@ QORIQ_CLK_PLL_DIV(4)>,
 		};
 
 		cluster4_core1_watchdog: wdt@c310000 {
-			compatible = "arm,sp805-wdt", "arm,primecell";
+			compatible = "arm,sp805", "arm,primecell";
 			reg = <0x0 0xc310000 0x0 0x1000>;
 			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 					    QORIQ_CLK_PLL_DIV(4)>,

-- 
2.30.2

[PATCH 6/7] arm64: dts: ls1028a: move PHY nodes to MDIO controller

From: Michael Walle <hidden>
Date: 2021-08-31 13:40:39

Move the PHY nodes from the network controller to the dedicated MDIO
controller. According to Vladimir Oltean direct MDIO access via the PF,
that is when the PHY is put under the "mdio" subnode, is defeatured and
in fact the latest reference manual isn't mentioning it anymore.

Suggested-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: Michael Walle <redacted>
---
 .../fsl-ls1028a-kontron-sl28-var1.dts         | 58 +++++++++----------
 .../fsl-ls1028a-kontron-sl28-var2.dts         | 17 ++----
 .../fsl-ls1028a-kontron-sl28-var4.dts         | 49 ++++++++--------
 .../freescale/fsl-ls1028a-kontron-sl28.dts    | 21 +++----
 .../boot/dts/freescale/fsl-ls1028a-rdb.dts    | 12 ++--
 5 files changed, 67 insertions(+), 90 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var1.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var1.dts
index e8d31279b7a3..836a9b7d8263 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var1.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var1.dts

@@ -8,7 +8,7 @@
  * None of the  four SerDes lanes are used by the module, instead they are
  * all led out to the carrier for customer use.
  *
- * Copyright (C) 2020 Michael Walle <michael@walle.cc>
+ * Copyright (C) 2021 Michael Walle <michael@walle.cc>
  *
  */

@@ -21,43 +21,39 @@ / {
 	compatible = "kontron,sl28-var1", "kontron,sl28", "fsl,ls1028a";
 };
 
+&enetc_mdio_pf3 {
+	/* Delete unused phy node */
+	/delete-node/ ethernet-phy@5;
+
+	phy0: ethernet-phy@4 {
+		reg = <0x4>;
+		eee-broken-1000t;
+		eee-broken-100tx;
+		qca,clk-out-frequency = <125000000>;
+		qca,clk-out-strength = <AR803X_STRENGTH_FULL>;
+		qca,keep-pll-enabled;
+		vddio-supply = <&vddio>;
+
+		vddio: vddio-regulator {
+			regulator-name = "VDDIO";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+		};
+
+		vddh: vddh-regulator {
+			regulator-name = "VDDH";
+		};
+	};
+};
+
 &enetc_port0 {
 	status = "disabled";
-	/*
-	 * Delete both the phy-handle to the old phy0 label as well as
-	 * the mdio node with the old phy node with the old phy0 label.
-	 */
+	/* Delete the phy-handle to the old phy0 label */
 	/delete-property/ phy-handle;
-	/delete-node/ mdio;
 };
 
 &enetc_port1 {
 	phy-handle = <&phy0>;
 	phy-connection-type = "rgmii-id";
 	status = "okay";
-
-	mdio {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		phy0: ethernet-phy@4 {
-			reg = <0x4>;
-			eee-broken-1000t;
-			eee-broken-100tx;
-			qca,clk-out-frequency = <125000000>;
-			qca,clk-out-strength = <AR803X_STRENGTH_FULL>;
-			qca,keep-pll-enabled;
-			vddio-supply = <&vddio>;
-
-			vddio: vddio-regulator {
-				regulator-name = "VDDIO";
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <1800000>;
-			};
-
-			vddh: vddh-regulator {
-				regulator-name = "VDDH";
-			};
-		};
-	};
 };

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var2.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var2.dts
index f6a79c8080d1..330e34f933a3 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var2.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var2.dts

@@ -5,7 +5,7 @@
  * This is for the network variant 2 which has two ethernet ports. These
  * ports are connected to the internal switch.
  *
- * Copyright (C) 2020 Michael Walle <michael@walle.cc>
+ * Copyright (C) 2021 Michael Walle <michael@walle.cc>
  *
  */

@@ -18,12 +18,6 @@ / {
 };
 
 &enetc_mdio_pf3 {
-	phy0: ethernet-phy@5 {
-		reg = <0x5>;
-		eee-broken-1000t;
-		eee-broken-100tx;
-	};
-
 	phy1: ethernet-phy@4 {
 		reg = <0x4>;
 		eee-broken-1000t;

@@ -34,14 +28,11 @@ phy1: ethernet-phy@4 {
 &enetc_port0 {
 	status = "disabled";
 	/*
-	 * In the base device tree the PHY was registered in the mdio
-	 * subnode as it is PHY for this port. On this module this PHY
-	 * is connected to a switch port instead and registered above.
-	 * Therefore, delete the mdio subnode as well as the phy-handle
-	 * property here.
+	 * In the base device tree the PHY at address 5 was assigned for
+	 * this port. On this module this PHY is connected to a switch
+	 * port instead. Therefore, delete the phy-handle property here.
 	 */
 	/delete-property/ phy-handle;
-	/delete-node/ mdio;
 };
 
 &enetc_port2 {

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var4.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var4.dts
index e65d1c477e2c..77ed0ebd2c75 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var4.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var4.dts

@@ -5,7 +5,7 @@
  * This is for the network variant 4 which has two ethernet ports. It
  * extends the base and provides one more port connected via RGMII.
  *
- * Copyright (C) 2019 Michael Walle <michael@walle.cc>
+ * Copyright (C) 2021 Michael Walle <michael@walle.cc>
  *
  */

@@ -18,33 +18,30 @@ / {
 	compatible = "kontron,sl28-var4", "kontron,sl28", "fsl,ls1028a";
 };
 
-&enetc_port1 {
-	phy-handle = <&phy1>;
-	phy-connection-type = "rgmii-id";
-	status = "okay";
+&enetc_mdio_pf3 {
+	phy1: ethernet-phy@4 {
+		reg = <0x4>;
+		eee-broken-1000t;
+		eee-broken-100tx;
+		qca,clk-out-frequency = <125000000>;
+		qca,clk-out-strength = <AR803X_STRENGTH_FULL>;
+		qca,keep-pll-enabled;
+		vddio-supply = <&vddio>;
 
-	mdio {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		phy1: ethernet-phy@4 {
-			reg = <0x4>;
-			eee-broken-1000t;
-			eee-broken-100tx;
-			qca,clk-out-frequency = <125000000>;
-			qca,clk-out-strength = <AR803X_STRENGTH_FULL>;
-			qca,keep-pll-enabled;
-			vddio-supply = <&vddio>;
-
-			vddio: vddio-regulator {
-				regulator-name = "VDDIO";
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <1800000>;
-			};
+		vddio: vddio-regulator {
+			regulator-name = "VDDIO";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+		};
 
-			vddh: vddh-regulator {
-				regulator-name = "VDDH";
-			};
+		vddh: vddh-regulator {
+			regulator-name = "VDDH";
 		};
 	};
 };
+
+&enetc_port1 {
+	phy-handle = <&phy1>;
+	phy-connection-type = "rgmii-id";
+	status = "okay";
+};

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts
index 2c6266991c38..b3e9c499e8b0 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts

@@ -2,7 +2,7 @@
 /*
  * Device Tree file for the Kontron SMARC-sAL28 board.
  *
- * Copyright (C) 2019 Michael Walle <michael@walle.cc>
+ * Copyright (C) 2021 Michael Walle <michael@walle.cc>
  *
  */

@@ -80,22 +80,19 @@ &duart1 {
 	status = "okay";
 };
 
+&enetc_mdio_pf3 {
+	phy0: ethernet-phy@5 {
+		reg = <0x5>;
+		eee-broken-1000t;
+		eee-broken-100tx;
+	};
+};
+
 &enetc_port0 {
 	phy-handle = <&phy0>;
 	phy-connection-type = "sgmii";
 	managed = "in-band-status";
 	status = "okay";
-
-	mdio {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		phy0: ethernet-phy@5 {
-			reg = <0x5>;
-			eee-broken-1000t;
-			eee-broken-100tx;
-		};
-	};
 };
 
 &esdhc {

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
index b0967b987f8a..ea11b1eb01f8 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts

@@ -197,6 +197,10 @@ &duart1 {
 };
 
 &enetc_mdio_pf3 {
+	sgmii_phy0: ethernet-phy@2 {
+		reg = <0x2>;
+	};
+
 	/* VSC8514 QSGMII quad PHY */
 	qsgmii_phy0: ethernet-phy@10 {
 		reg = <0x10>;

@@ -220,14 +224,6 @@ &enetc_port0 {
 	phy-connection-type = "sgmii";
 	managed = "in-band-status";
 	status = "okay";
-
-	mdio {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		sgmii_phy0: ethernet-phy@2 {
-			reg = <0x2>;
-		};
-	};
 };
 
 &enetc_port2 {

-- 
2.30.2

[PATCH 7/7] arm64: dts: ls1028a: use phy-mode instead of phy-connection-type

From: Michael Walle <hidden>
Date: 2021-08-31 13:40:40

In linux both are identical, phy-mode is used more often, though. Also
for the ls1028a both phy-connection-type and phy-mode was used, one for
the enetc nodes and the other for the switch nodes. Unify them. But the
main reason for this is that the device tree files can be shared with
the u-boot ones; there the enetc driver only supports the "phy-mode"
property.

Suggested-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: Michael Walle <redacted>
---
 arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var1.dts | 2 +-
 arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var4.dts | 2 +-
 arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts      | 2 +-
 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts               | 2 +-
 arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts               | 2 +-
 5 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var1.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var1.dts
index 836a9b7d8263..7cd29ab970d9 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var1.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var1.dts

@@ -54,6 +54,6 @@ &enetc_port0 {
 
 &enetc_port1 {
 	phy-handle = <&phy0>;
-	phy-connection-type = "rgmii-id";
+	phy-mode = "rgmii-id";
 	status = "okay";
 };

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var4.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var4.dts
index 77ed0ebd2c75..9b5e92fb753e 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var4.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var4.dts

@@ -42,6 +42,6 @@ vddh: vddh-regulator {
 
 &enetc_port1 {
 	phy-handle = <&phy1>;
-	phy-connection-type = "rgmii-id";
+	phy-mode = "rgmii-id";
 	status = "okay";
 };

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts
index b3e9c499e8b0..d74e738e4070 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts

@@ -90,7 +90,7 @@ phy0: ethernet-phy@5 {
 
 &enetc_port0 {
 	phy-handle = <&phy0>;
-	phy-connection-type = "sgmii";
+	phy-mode = "sgmii";
 	managed = "in-band-status";
 	status = "okay";
 };

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
index f36f87858aef..6e2a1da662fb 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts

@@ -320,7 +320,7 @@ mux: mux-controller {
 
 &enetc_port1 {
 	phy-handle = <&qds_phy1>;
-	phy-connection-type = "rgmii-id";
+	phy-mode = "rgmii-id";
 	status = "okay";
 };

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
index ea11b1eb01f8..7719f44bcaed 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts

@@ -221,7 +221,7 @@ qsgmii_phy3: ethernet-phy@13 {
 
 &enetc_port0 {
 	phy-handle = <&sgmii_phy0>;
-	phy-connection-type = "sgmii";
+	phy-mode = "sgmii";
 	managed = "in-band-status";
 	status = "okay";
 };

-- 
2.30.2

[PATCH 5/7] arm64: dts: ls1028a: disable usb controller by default

From: Michael Walle <hidden>
Date: 2021-08-31 13:40:43

One of the last devices which are enabled by default are the USB
controllers. Although the pins are not multi-function pins, some boards
might not use USB at all. Apply the "disabled-by-default" style also for
the USB controllers and enable the controllers in the actual device tree
of the boards.

Signed-off-by: Michael Walle <redacted>
---
 .../arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts | 8 ++++++++
 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts         | 8 ++++++++
 arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts         | 5 +++++
 arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi            | 2 ++
 4 files changed, 23 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts
index a92ecb331cdc..2c6266991c38 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts

@@ -309,3 +309,11 @@ eeprom@50 {
 &lpuart1 {
 	status = "okay";
 };
+
+&usb0 {
+	status = "okay";
+};
+
+&usb1 {
+	status = "okay";
+};

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
index bfd14b64567e..f36f87858aef 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts

@@ -335,3 +335,11 @@ &sai1 {
 &sata {
 	status = "okay";
 };
+
+&usb0 {
+	status = "okay";
+};
+
+&usb1 {
+	status = "okay";
+};

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
index d7b527272500..b0967b987f8a 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts

@@ -287,6 +287,11 @@ &sata {
 	status = "okay";
 };
 
+&usb0 {
+	status = "okay";
+};
+
 &usb1 {
 	dr_mode = "otg";
+	status = "okay";
 };

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
index 876dea668a90..c10c84d9495d 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi

@@ -585,6 +585,7 @@ usb0: usb@3100000 {
 			snps,dis_rxdet_inp3_quirk;
 			snps,quirk-frame-length-adjustment = <0x20>;
 			snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
+			status = "disabled";
 		};
 
 		usb1: usb@3110000 {

@@ -595,6 +596,7 @@ usb1: usb@3110000 {
 			snps,dis_rxdet_inp3_quirk;
 			snps,quirk-frame-length-adjustment = <0x20>;
 			snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
+			status = "disabled";
 		};
 
 		sata: sata@3200000 {

-- 
2.30.2

Re: [PATCH 7/7] arm64: dts: ls1028a: use phy-mode instead of phy-connection-type

From: Vladimir Oltean <vladimir.oltean@nxp.com>
Date: 2021-08-31 14:00:20

On Tue, Aug 31, 2021 at 03:40:13PM +0200, Michael Walle wrote:

In linux both are identical, phy-mode is used more often, though. Also
for the ls1028a both phy-connection-type and phy-mode was used, one for
the enetc nodes and the other for the switch nodes. Unify them. But the
main reason for this is that the device tree files can be shared with
the u-boot ones; there the enetc driver only supports the "phy-mode"
property.

Suggested-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: Michael Walle <redacted>
---

Actually that is not really a valid reason in itself for this change.
The enetc U-Boot driver is perhaps a bit silly in that it calls
ofnode_read_string(dev_ofnode(dev), "phy-mode") manually, especially
since right below, it uses dm_eth_phy_connect() which searches for both.

So we are artificially restricting what we support. It would be fine to
do the dm_eth_phy_connect first, then use phy->interface for enetc_start_pcs().

Anyway, I do not mind the patch at all.

Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>

Re: [PATCH 7/7] arm64: dts: ls1028a: use phy-mode instead of phy-connection-type

From: Michael Walle <hidden>
Date: 2021-08-31 14:06:27

Am 2021-08-31 15:59, schrieb Vladimir Oltean:

On Tue, Aug 31, 2021 at 03:40:13PM +0200, Michael Walle wrote:

quoted

In linux both are identical, phy-mode is used more often, though. Also
for the ls1028a both phy-connection-type and phy-mode was used, one for
the enetc nodes and the other for the switch nodes. Unify them. But the
main reason for this is that the device tree files can be shared with
the u-boot ones; there the enetc driver only supports the "phy-mode"
property.

Suggested-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: Michael Walle <redacted>
---

Actually that is not really a valid reason in itself for this change.
The enetc U-Boot driver is perhaps a bit silly in that it calls
ofnode_read_string(dev_ofnode(dev), "phy-mode") manually, especially
since right below, it uses dm_eth_phy_connect() which searches for both.

So we are artificially restricting what we support. It would be fine to
do the dm_eth_phy_connect first, then use phy->interface for enetc_start_pcs().

You mean in u-boot. I had a patch for it, but because you suggested
to convert it to the new property name, it isn't really needed anyway.
u-boot is just using the device trees within its source tree, so I
didn't care anymore ;)

Anyway, I do not mind the patch at all.

Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>

Thanks!

-michael

Re: [PATCH 6/7] arm64: dts: ls1028a: move PHY nodes to MDIO controller

From: Vladimir Oltean <vladimir.oltean@nxp.com>
Date: 2021-08-31 14:07:13

On Tue, Aug 31, 2021 at 03:40:12PM +0200, Michael Walle wrote:

Move the PHY nodes from the network controller to the dedicated MDIO
controller. According to Vladimir Oltean direct MDIO access via the PF,
that is when the PHY is put under the "mdio" subnode, is defeatured and
in fact the latest reference manual isn't mentioning it anymore.

Suggested-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: Michael Walle <redacted>
---

Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>

Re: [PATCH 5/7] arm64: dts: ls1028a: disable usb controller by default

From: Vladimir Oltean <vladimir.oltean@nxp.com>
Date: 2021-08-31 14:08:47

On Tue, Aug 31, 2021 at 03:40:11PM +0200, Michael Walle wrote:

One of the last devices which are enabled by default are the USB
controllers. Although the pins are not multi-function pins, some boards
might not use USB at all. Apply the "disabled-by-default" style also for
the USB controllers and enable the controllers in the actual device tree
of the boards.

Signed-off-by: Michael Walle <redacted>
---

Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>

Re: [PATCH 0/7] arm64: dts: ls1028: GPU support and cleanups

From: Shawn Guo <shawnguo@kernel.org>
Date: 2021-10-04 13:08:46

On Tue, Aug 31, 2021 at 03:40:06PM +0200, Michael Walle wrote:

In an attempt to unify u-boot's and linux' device tree for the LS1028A SoC
we first need to clean up some network related stuff. Vladimir suggested to
move the Ethernet PHYs into the MDIO controller node, which is already the
case for u-boot's device tree. Further we unify the use of phy-mode and
phy-connection-type. Both have the same meaning, but phy-mode is used more
often in the kernel and for the ls1028a both were used. Replace
phy-connection-type with phy-mode.

Further move all the nodes which belongs to the CCSR into the /soc node.
These are the Mali display conntroller and its associated pixel clock PLL.
Finally, add the GPU node for the etnaviv driver under /soc.

Michael Walle (7):
  arm64: dts: ls1028a: move pixel clock pll into /soc
  arm64: dts: ls1028a: move Mali DP500 node into /soc
  arm64: dts: ls1028a: add Vivante GPU node
  arm64: dts: freescale: fix arm,sp805 compatible string
  arm64: dts: ls1028a: disable usb controller by default
  arm64: dts: ls1028a: move PHY nodes to MDIO controller
  arm64: dts: ls1028a: use phy-mode instead of phy-connection-type

Applied all, except #4 which had been picked up separately.

Shawn

RE: [PATCH 2/7] arm64: dts: ls1028a: move Mali DP500 node into /soc

From: Leo Li <hidden>
Date: 2022-01-20 08:06:54

-----Original Message-----
From: Michael Walle <redacted>
Sent: Tuesday, August 31, 2021 9:40 PM
To: linux-arm-kernel@lists.infradead.org; devicetree@vger.kernel.org; linux-
kernel@vger.kernel.org
Cc: Shawn Guo <shawnguo@kernel.org>; Leo Li <redacted>; Rob
Herring [off-list ref]; Vladimir Oltean [off-list ref];
Michael Walle [off-list ref]
Subject: [PATCH 2/7] arm64: dts: ls1028a: move Mali DP500 node into /soc

Move it inside the /soc subnode because it is part of the CCSR space.

I just noticed that the dp0_out label has been changed to dpi0_out besides the move.  Is this an intentional change or a typo?  If intentional we probably should mention it, otherwise we should change it back as it is breaking build for off-tree patch that uses the label.

quoted hunk

Signed-off-by: Michael Walle <redacted>
---
 .../arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 41 ++++++++++---------
 1 file changed, 21 insertions(+), 20 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi

b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
index 9a65a7118faa..92e4f004c1c2 100644

--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi

@@ -793,6 +793,27 @@ QORIQ_CLK_PLL_DIV(16)>,
 			clock-names = "wdog_clk", "apb_pclk";
 		};

+		malidp0: display@f080000 {
+			compatible = "arm,mali-dp500";
+			reg = <0x0 0xf080000 0x0 0x10000>;
+			interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>,
+				     <0 223 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "DE", "SE";
+			clocks = <&dpclk>,
+				 <&clockgen QORIQ_CLK_HWACCEL 2>,
+				 <&clockgen QORIQ_CLK_HWACCEL 2>,
+				 <&clockgen QORIQ_CLK_HWACCEL 2>;
+			clock-names = "pxlclk", "mclk", "aclk", "pclk";
+			arm,malidp-output-port-lines = /bits/ 8 <8 8 8>;
+			arm,malidp-arqos-value = <0xd000d000>;
+
+			port {
+				dpi0_out: endpoint {
+
+				};
+			};
+		};
+
 		sai1: audio-controller@f100000 {
 			#sound-dai-cells = <0>;
 			compatible = "fsl,vf610-sai";

@@ -1139,24 +1160,4 @@ ftm_alarm0: timer@2800000 {
 		};
 	};

-	malidp0: display@f080000 {
-		compatible = "arm,mali-dp500";
-		reg = <0x0 0xf080000 0x0 0x10000>;
-		interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 223 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-names = "DE", "SE";
-		clocks = <&dpclk>,
-			 <&clockgen QORIQ_CLK_HWACCEL 2>,
-			 <&clockgen QORIQ_CLK_HWACCEL 2>,
-			 <&clockgen QORIQ_CLK_HWACCEL 2>;
-		clock-names = "pxlclk", "mclk", "aclk", "pclk";
-		arm,malidp-output-port-lines = /bits/ 8 <8 8 8>;
-		arm,malidp-arqos-value = <0xd000d000>;
-
-		port {
-			dp0_out: endpoint {
-
-			};
-		};
-	};
 };
--

2.30.2

Re: [PATCH 2/7] arm64: dts: ls1028a: move Mali DP500 node into /soc

From: Michael Walle <hidden>
Date: 2022-01-20 08:17:43

Am 2022-01-20 09:06, schrieb Leo Li:

quoted

-----Original Message-----
From: Michael Walle <redacted>
Sent: Tuesday, August 31, 2021 9:40 PM
To: linux-arm-kernel@lists.infradead.org; devicetree@vger.kernel.org; linux-
kernel@vger.kernel.org
Cc: Shawn Guo <shawnguo@kernel.org>; Leo Li <redacted>; Rob
Herring [off-list ref]; Vladimir Oltean [off-list ref];
Michael Walle [off-list ref]
Subject: [PATCH 2/7] arm64: dts: ls1028a: move Mali DP500 node into /soc

Move it inside the /soc subnode because it is part of the CCSR space.

I just noticed that the dp0_out label has been changed to dpi0_out
besides the move.  Is this an intentional change or a typo?  If
intentional we probably should mention it, otherwise we should change
it back as it is breaking build for off-tree patch that uses the
label.

It's intentional, because dp0_out might sound like displayport. And
from what I've found the output is a display pixel interface, hence dpi.

I agree, that this should have been two patches, must have slipped.
But this series was merged months ago, so we can't change anything
anymore.

Besides, given the fact that there is no support for the DisplayPort
PHY in upstream (yet, I'm working on that), I doubt there are any
out-of-tree device trees, which don't use the proprietary NXP
driver.

Also, if there is an out-of-tree device tree, it should be easy
enough for NXP to change that :)

-michael

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