@@ -1,32 +0,0 @@-* Cadence Universal Flash Storage (UFS) Controller--UFS nodes are defined to describe on-chip UFS host controllers.-Each UFS controller instance should have its own node.-Please see the ufshcd-pltfrm.txt for a list of all available properties.--Required properties:-- compatible : Compatible list, contains one of the following controllers:- "cdns,ufshc" - Generic CDNS HCI,- "cdns,ufshc-m31-16nm" - CDNS UFS HC + M31 16nm PHY- complemented with the JEDEC version:- "jedec,ufs-2.0"--- reg : Address and length of the UFS register set.-- interrupts : One interrupt mapping.-- freq-table-hz : Clock frequency table.- See the ufshcd-pltfrm.txt for details.-- clocks : List of phandle and clock specifier pairs.-- clock-names : List of clock input name strings sorted in the same- order as the clocks property. "core_clk" is mandatory.- Depending on a type of a PHY,- the "phy_clk" clock can also be added, if needed.--Example:- ufs@fd030000 {- compatible = "cdns,ufshc", "jedec,ufs-2.0";- reg = <0xfd030000 0x10000>;- interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH>;- freq-table-hz = <0 0>, <0 0>;- clocks = <&ufs_core_clk>, <&ufs_phy_clk>;- clock-names = "core_clk", "phy_clk";- };
@@ -0,0 +1,80 @@+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)+%YAML1.2+---+$id:http://devicetree.org/schemas/ufs/cdns,ufshc.yaml#+$schema:http://devicetree.org/meta-schemas/core.yaml#++title:Cadence Universal Flash Storage (UFS) Controller++maintainers:+-Dhananjay Kangude <dkangude@cadence.com>++description:+UFS nodes are defined to describe on-chip Cadence UFS host controllers.+Each UFS controller instance should have its own node.++properties:+compatible:+oneOf:+-items:+-enum:+-cdns,ufshc+-cdns,ufshc-m31-16nm+-const:jedec,ufs-2.0+-items:+-const:jedec,ufs-2.0++reg:+items:+-description:UFS controller register set++interrupts:+maxItems:1++clocks:+minItems:1+items:+-description:Description of core_clk+-description:Description of phy_clk+-description:Description of ref_clk++clock-names:+minItems:1+items:+-const:core_clk+-const:phy_clk+-const:ref_clk++freq-table-hz:+$ref:/schemas/types.yaml#/definitions/uint64-matrix+description:+Clock frequency table.+See the ufshcd-pltfrm.txt for details.++dma-coherent:true++required:+-compatible+-reg+-interrupts+-freq-table-hz+-clocks+-clock-names++additionalProperties:false+unevaluatedProperties:false++examples:+-|+#include <dt-bindings/interrupt-controller/irq.h>+#include <dt-bindings/interrupt-controller/arm-gic.h>++ufs:ufs@fd030000 {+compatible = "cdns,ufshc", "jedec,ufs-2.0";+reg = <0xfd030000 0x10000>;+interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH>;+freq-table-hz = <0 0>;+clocks = <&ufs_core_clk>;+clock-names = "core_clk";+};+
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/ufs/ti,j721e-ufs.example.dt.yaml: ufs@4000: 'power-domains' does not match any of the regexes: 'pinctrl-[0-9]+'
From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/ufs/cdns,ufshc.yaml
doc reference errors (make refcheckdocs):
Documentation/devicetree/bindings/ufs/ti,j721e-ufs.yaml: Documentation/devicetree/bindings/ufs/cdns,ufshc.txt
See https://patchwork.ozlabs.org/patch/1521296
This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.
@@ -1,32 +0,0 @@-* Cadence Universal Flash Storage (UFS) Controller--UFS nodes are defined to describe on-chip UFS host controllers.-Each UFS controller instance should have its own node.-Please see the ufshcd-pltfrm.txt for a list of all available properties.--Required properties:-- compatible : Compatible list, contains one of the following controllers:- "cdns,ufshc" - Generic CDNS HCI,- "cdns,ufshc-m31-16nm" - CDNS UFS HC + M31 16nm PHY- complemented with the JEDEC version:- "jedec,ufs-2.0"--- reg : Address and length of the UFS register set.-- interrupts : One interrupt mapping.-- freq-table-hz : Clock frequency table.- See the ufshcd-pltfrm.txt for details.-- clocks : List of phandle and clock specifier pairs.-- clock-names : List of clock input name strings sorted in the same- order as the clocks property. "core_clk" is mandatory.- Depending on a type of a PHY,- the "phy_clk" clock can also be added, if needed.--Example:- ufs@fd030000 {- compatible = "cdns,ufshc", "jedec,ufs-2.0";- reg = <0xfd030000 0x10000>;- interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH>;- freq-table-hz = <0 0>, <0 0>;- clocks = <&ufs_core_clk>, <&ufs_phy_clk>;- clock-names = "core_clk", "phy_clk";- };
@@ -0,0 +1,80 @@+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)+%YAML1.2+---+$id:http://devicetree.org/schemas/ufs/cdns,ufshc.yaml#+$schema:http://devicetree.org/meta-schemas/core.yaml#++title:Cadence Universal Flash Storage (UFS) Controller++maintainers:+-Dhananjay Kangude <dkangude@cadence.com>++description:+UFS nodes are defined to describe on-chip Cadence UFS host controllers.+Each UFS controller instance should have its own node.++properties:+compatible:+oneOf:+-items:+-enum:+-cdns,ufshc+-cdns,ufshc-m31-16nm+-const:jedec,ufs-2.0+-items:+-const:jedec,ufs-2.0++reg:+items:+-description:UFS controller register set++interrupts:+maxItems:1++clocks:+minItems:1+items:+-description:Description of core_clk+-description:Description of phy_clk+-description:Description of ref_clk++clock-names:+minItems:1+items:+-const:core_clk+-const:phy_clk+-const:ref_clk++freq-table-hz:+$ref:/schemas/types.yaml#/definitions/uint64-matrix+description:+Clock frequency table.+See the ufshcd-pltfrm.txt for details.++dma-coherent:true++required:+-compatible+-reg+-interrupts+-freq-table-hz+-clocks+-clock-names++additionalProperties:false+unevaluatedProperties:false++examples:+-|+#include <dt-bindings/interrupt-controller/irq.h>+#include <dt-bindings/interrupt-controller/arm-gic.h>++ufs:ufs@fd030000 {+compatible = "cdns,ufshc", "jedec,ufs-2.0";+reg = <0xfd030000 0x10000>;+interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH>;+freq-table-hz = <0 0>;+clocks = <&ufs_core_clk>;+clock-names = "core_clk";+};+
@@ -50,7 +50,7 @@ patternProperties:type:objectdescription:|Cadence UFS controller node must be the child node. Refer-Documentation/devicetree/bindings/ufs/cdns,ufshc.txt for binding+Documentation/devicetree/bindings/ufs/cdns,ufshc.yaml for bindingdocumentation of child nodeadditionalProperties:false
From: Rob Herring <robh@kernel.org> Date: 2021-09-07 18:54:48
On Thu, Sep 02, 2021 at 08:37:54AM +0200, Dhananjay Kangude wrote:
1.Converted bindings into yaml format for Cadence UFS host controller
2.Modified reference to cdns,ufshc.txt tp cdns,ufshc.yaml
3.Removed power,domain property from ti,j721e-ufs.yaml as it is not required
Maybe not required, but should be allowed which is still not the case.
@@ -1,32 +0,0 @@-* Cadence Universal Flash Storage (UFS) Controller--UFS nodes are defined to describe on-chip UFS host controllers.-Each UFS controller instance should have its own node.-Please see the ufshcd-pltfrm.txt for a list of all available properties.--Required properties:-- compatible : Compatible list, contains one of the following controllers:- "cdns,ufshc" - Generic CDNS HCI,- "cdns,ufshc-m31-16nm" - CDNS UFS HC + M31 16nm PHY- complemented with the JEDEC version:- "jedec,ufs-2.0"--- reg : Address and length of the UFS register set.-- interrupts : One interrupt mapping.-- freq-table-hz : Clock frequency table.- See the ufshcd-pltfrm.txt for details.-- clocks : List of phandle and clock specifier pairs.-- clock-names : List of clock input name strings sorted in the same- order as the clocks property. "core_clk" is mandatory.- Depending on a type of a PHY,- the "phy_clk" clock can also be added, if needed.--Example:- ufs@fd030000 {- compatible = "cdns,ufshc", "jedec,ufs-2.0";- reg = <0xfd030000 0x10000>;- interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH>;- freq-table-hz = <0 0>, <0 0>;- clocks = <&ufs_core_clk>, <&ufs_phy_clk>;- clock-names = "core_clk", "phy_clk";- };
@@ -0,0 +1,80 @@+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)+%YAML1.2+---+$id:http://devicetree.org/schemas/ufs/cdns,ufshc.yaml#+$schema:http://devicetree.org/meta-schemas/core.yaml#++title:Cadence Universal Flash Storage (UFS) Controller++maintainers:+-Dhananjay Kangude <dkangude@cadence.com>++description:+UFS nodes are defined to describe on-chip Cadence UFS host controllers.+Each UFS controller instance should have its own node.++properties:+compatible:+oneOf:+-items:+-enum:+-cdns,ufshc+-cdns,ufshc-m31-16nm+-const:jedec,ufs-2.0+-items:+-const:jedec,ufs-2.0++reg:+items:+-description:UFS controller register set
Not a useful description. Just 'maxItems: 1'.
quoted hunk
++ interrupts:+ maxItems: 1++ clocks:+ minItems: 1+ items:+ - description: Description of core_clk+ - description: Description of phy_clk+ - description: Description of ref_clk
'Description of core_clk'?
ref_clk was not documented. Okay to add, but mention why in the commit
msg.
@@ -50,7 +50,7 @@ patternProperties:type:objectdescription:|Cadence UFS controller node must be the child node. Refer-Documentation/devicetree/bindings/ufs/cdns,ufshc.txt for binding+Documentation/devicetree/bindings/ufs/cdns,ufshc.yaml for bindingdocumentation of child nodeadditionalProperties:false
On Thu, Sep 02, 2021 at 08:37:54AM +0200, Dhananjay Kangude wrote:
quoted
1.Converted bindings into yaml format for Cadence UFS host controller
2.Modified reference to cdns,ufshc.txt tp cdns,ufshc.yaml 3.Removed
power,domain property from ti,j721e-ufs.yaml as it is not required
Maybe not required, but should be allowed which is still not the case.
I got it. I will add the power,domain property as an optional in ufs and retain ti,j721-ufs.yaml in original form.
@@ -1,32 +0,0 @@-* Cadence Universal Flash Storage (UFS) Controller--UFS nodes are defined to describe on-chip UFS host controllers.-Each UFS controller instance should have its own node.-Please see the ufshcd-pltfrm.txt for a list of all available properties.--Required properties:-- compatible : Compatible list, contains one of the following controllers:- "cdns,ufshc" - Generic CDNS HCI,- "cdns,ufshc-m31-16nm" - CDNS UFS HC + M31 16nm
PHY
quoted
- complemented with the JEDEC version:
- "jedec,ufs-2.0"
-
-- reg : Address and length of the UFS register set.
-- interrupts : One interrupt mapping.
-- freq-table-hz : Clock frequency table.
- See the ufshcd-pltfrm.txt for details.
-- clocks : List of phandle and clock specifier pairs.
-- clock-names : List of clock input name strings sorted in the same
- order as the clocks property. "core_clk" is mandatory.
- Depending on a type of a PHY,
- the "phy_clk" clock can also be added, if needed.
-
-Example:
- ufs@fd030000 {
- compatible = "cdns,ufshc", "jedec,ufs-2.0";
- reg = <0xfd030000 0x10000>;
- interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH>;
- freq-table-hz = <0 0>, <0 0>;
- clocks = <&ufs_core_clk>, <&ufs_phy_clk>;
- clock-names = "core_clk", "phy_clk";
- };
+EAQrSfmirkkVpEHrPgh4$++title: Cadence Universal Flash Storage (UFS) Controller++maintainers:+ - Dhananjay Kangude <dkangude@cadence.com>++description:+ UFS nodes are defined to describe on-chip Cadence UFS host controllers.+ Each UFS controller instance should have its own node.++properties:+ compatible:+ oneOf:+ - items:+ - enum:+ - cdns,ufshc+ - cdns,ufshc-m31-16nm+ - const: jedec,ufs-2.0+ - items:+ - const: jedec,ufs-2.0++ reg:+ items:+ - description: UFS controller register set
Not a useful description. Just 'maxItems: 1'.
I agree. I will change the property details.
quoted
++ interrupts:+ maxItems: 1++ clocks:+ minItems: 1+ items:+ - description: Description of core_clk+ - description: Description of phy_clk+ - description: Description of ref_clk
'Description of core_clk'?
OK. I will change it.
ref_clk was not documented. Okay to add, but mention why in the commit
msg.
The ref_clk is used by ufs spec to decide ufs device reference clock and it is part of ufs framework.
Usually SoC vendors fix this value by using this property used by core framework.
The details are already mentioned in Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt
I have tried with different ref as single array but it seems not compatible.
The freq-table-hz property need the values in 2D array format.
for example:
freq-table-hz = <250000000 250000000>, <19200000 19200000>, <19200000 19200000>;
Could you suggest what type suits the requirement. Thanks.
quoted
+ description:+ Clock frequency table.+ See the ufshcd-pltfrm.txt for details.++ dma-coherent: true++required:+ - compatible+ - reg+ - interrupts+ - freq-table-hz+ - clocks+ - clock-names++additionalProperties: false+unevaluatedProperties: false
@@ -50,7 +50,7 @@ patternProperties:type:objectdescription:|Cadence UFS controller node must be the child node. Refer-Documentation/devicetree/bindings/ufs/cdns,ufshc.txt for binding+Documentation/devicetree/bindings/ufs/cdns,ufshc.yaml for+bindingdocumentation of child nodeadditionalProperties:false
Hi Rob,
This is with respect to your comment on the right type for property freq-table-hz.
I have tried different combinations but it seems not compatible with property.
The param freq-table-hz have multiple pair of frequencies in <Min Max> format which
needed to decide operating frequencies in the same order of clocks property.
I would appreciate if you provide some suggestion for correct type.
Thanks
Dhananjay
-----Original Message-----
From: Dhananjay Vilasrao Kangude
Sent: Thursday, September 9, 2021 5:38 PM
To: Rob Herring <robh@kernel.org>
Cc: devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; Milind Parab
[off-list ref]; vigneshr@ti.com; kishon@ti.com
Subject: RE: [PATCH v2] dt-bindings: ufshc: cdns: convert bindings for
Cadence UFS host controller
quoted
On Thu, Sep 02, 2021 at 08:37:54AM +0200, Dhananjay Kangude wrote:
quoted
1.Converted bindings into yaml format for Cadence UFS host
controller 2.Modified reference to cdns,ufshc.txt tp cdns,ufshc.yaml
3.Removed power,domain property from ti,j721e-ufs.yaml as it is not
required
Maybe not required, but should be allowed which is still not the case.
I got it. I will add the power,domain property as an optional in ufs and retain
ti,j721-ufs.yaml in original form.
@@ -1,32 +0,0 @@-* Cadence Universal Flash Storage (UFS) Controller--UFS nodes are defined to describe on-chip UFS host controllers.-Each UFS controller instance should have its own node.-Please see the ufshcd-pltfrm.txt for a list of all available properties.--Required properties:-- compatible : Compatible list, contains one of the following
- complemented with the JEDEC version:
- "jedec,ufs-2.0"
-
-- reg : Address and length of the UFS register set.
-- interrupts : One interrupt mapping.
-- freq-table-hz : Clock frequency table.
- See the ufshcd-pltfrm.txt for details.
-- clocks : List of phandle and clock specifier pairs.
-- clock-names : List of clock input name strings sorted in the same
- order as the clocks property. "core_clk" is mandatory.
- Depending on a type of a PHY,
- the "phy_clk" clock can also be added, if needed.
-
-Example:
- ufs@fd030000 {
- compatible = "cdns,ufshc", "jedec,ufs-2.0";
- reg = <0xfd030000 0x10000>;
- interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH>;
- freq-table-hz = <0 0>, <0 0>;
- clocks = <&ufs_core_clk>, <&ufs_phy_clk>;
- clock-names = "core_clk", "phy_clk";
- };
+EAQrSfmirkkVpEHrPgh4$++title: Cadence Universal Flash Storage (UFS) Controller++maintainers:+ - Dhananjay Kangude <dkangude@cadence.com>++description:+ UFS nodes are defined to describe on-chip Cadence UFS host
controllers.
quoted
quoted
+ Each UFS controller instance should have its own node.++properties:+ compatible:+ oneOf:+ - items:+ - enum:+ - cdns,ufshc+ - cdns,ufshc-m31-16nm+ - const: jedec,ufs-2.0+ - items:+ - const: jedec,ufs-2.0++ reg:+ items:+ - description: UFS controller register set
Not a useful description. Just 'maxItems: 1'.
I agree. I will change the property details.
quoted
quoted
++ interrupts:+ maxItems: 1++ clocks:+ minItems: 1+ items:+ - description: Description of core_clk+ - description: Description of phy_clk+ - description: Description of ref_clk
'Description of core_clk'?
OK. I will change it.
quoted
ref_clk was not documented. Okay to add, but mention why in the commit
msg.
The ref_clk is used by ufs spec to decide ufs device reference clock and it is
part of ufs framework.
Usually SoC vendors fix this value by using this property used by core
framework.
The details are already mentioned in
Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt
I have tried with different ref as single array but it seems not compatible.
The freq-table-hz property need the values in 2D array format.
for example:
freq-table-hz = <250000000 250000000>, <19200000 19200000>, <19200000
19200000>;
Could you suggest what type suits the requirement. Thanks.
quoted
quoted
+ description:+ Clock frequency table.+ See the ufshcd-pltfrm.txt for details.++ dma-coherent: true++required:+ - compatible+ - reg+ - interrupts+ - freq-table-hz+ - clocks+ - clock-names++additionalProperties: false+unevaluatedProperties: false
@@ -50,7 +50,7 @@ patternProperties:type:objectdescription:|Cadence UFS controller node must be the child node. Refer-Documentation/devicetree/bindings/ufs/cdns,ufshc.txt for binding+Documentation/devicetree/bindings/ufs/cdns,ufshc.yaml for+bindingdocumentation of child nodeadditionalProperties:false