@@ -1,21 +0,0 @@-Device Tree bindings for MVEBU SDRAM controllers--The Marvell EBU SoCs all have a SDRAM controller. The SDRAM controller-differs from one SoC variant to another, but they also share a number-of commonalities.--For now, this Device Tree binding documentation only documents the-Armada XP SDRAM controller.--Required properties:-- - compatible: for Armada XP, "marvell,armada-xp-sdram-controller"- - reg: a resource specifier for the register space, which should- include all SDRAM controller registers as per the datasheet.--Example:--sdramc@1400 {- compatible = "marvell,armada-xp-sdram-controller";- reg = <0x1400 0x500>;-};
From: Krzysztof Kozlowski <hidden> Date: 2021-08-17 09:40:16
Include dt-bindings for Marvell Armada XP SDRAM and L2 cache ECC in the
EDAC-ARMADA entry.
Signed-off-by: Krzysztof Kozlowski <redacted>
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
@@ -1,21 +0,0 @@-Device Tree bindings for MVEBU SDRAM controllers--The Marvell EBU SoCs all have a SDRAM controller. The SDRAM controller-differs from one SoC variant to another, but they also share a number-of commonalities.--For now, this Device Tree binding documentation only documents the-Armada XP SDRAM controller.
Please keep the description, otherwise it would be confusing why the binding is
named marvell,mvebu-sdram-controller.yaml although it (currenly) only applies to
the Armada XP.
Jan
-
-Required properties:
-
- - compatible: for Armada XP, "marvell,armada-xp-sdram-controller"
- - reg: a resource specifier for the register space, which should
- include all SDRAM controller registers as per the datasheet.
-
-Example:
-
-sdramc@1400 {
- compatible = "marvell,armada-xp-sdram-controller";
- reg = <0x1400 0x500>;
-};
@@ -1,21 +0,0 @@-Device Tree bindings for MVEBU SDRAM controllers--The Marvell EBU SoCs all have a SDRAM controller. The SDRAM controller-differs from one SoC variant to another, but they also share a number-of commonalities.--For now, this Device Tree binding documentation only documents the-Armada XP SDRAM controller.
Please keep the description, otherwise it would be confusing why the binding is
named marvell,mvebu-sdram-controller.yaml although it (currenly) only applies to
the Armada XP.
The description does not explain why it only documents Armada XP, so it
just duplicates what is in "compatible" part of bindings. How is the
confusion removed by saying "we document currently only Armada XP"? What
changes?
The entire description (with first paragraph) might make it a derivative
work, so I would need Ack or SoB from author to relicense it (Cc: Thomas
Petazzoni).
Best regards,
Krzysztof
@@ -1,21 +0,0 @@-Device Tree bindings for MVEBU SDRAM controllers--The Marvell EBU SoCs all have a SDRAM controller. The SDRAM controller-differs from one SoC variant to another, but they also share a number-of commonalities.--For now, this Device Tree binding documentation only documents the-Armada XP SDRAM controller.
Please keep the description, otherwise it would be confusing why the binding is
named marvell,mvebu-sdram-controller.yaml although it (currenly) only applies to
the Armada XP.
The description does not explain why it only documents Armada XP, so it
just duplicates what is in "compatible" part of bindings. How is the
confusion removed by saying "we document currently only Armada XP"? What
changes?
Then perhaps the binding should be named marvell,armada-xp-sdram-
controller.yaml? It find it unlikely that support for the other SoC's
controllers will be added, given their age.
Jan
The entire description (with first paragraph) might make it a derivative
work, so I would need Ack or SoB from author to relicense it (Cc: Thomas
Petazzoni).
Best regards,
Krzysztof
@@ -1,21 +0,0 @@-Device Tree bindings for MVEBU SDRAM controllers--The Marvell EBU SoCs all have a SDRAM controller. The SDRAM controller-differs from one SoC variant to another, but they also share a number-of commonalities.--For now, this Device Tree binding documentation only documents the-Armada XP SDRAM controller.
Please keep the description, otherwise it would be confusing why the binding is
named marvell,mvebu-sdram-controller.yaml although it (currenly) only applies to
the Armada XP.
The description does not explain why it only documents Armada XP, so it
just duplicates what is in "compatible" part of bindings. How is the
confusion removed by saying "we document currently only Armada XP"? What
changes?
Then perhaps the binding should be named marvell,armada-xp-sdram-
controller.yaml? It find it unlikely that support for the other SoC's
controllers will be added, given their age.
Sure, could be like this but there is no confusion here and no need to
fix anything. It is understandable and common to name bindings file as
general (e.g. for group of devices) even though only limited amount of
devices are currently documented/described. It's almost everywhere like
this, when the bindings are not complete. I don't see where is the
confusion.
Look at: arm/marvell/armada-cpu-reset.txt which mentions several SoCs
while only three compatibles are documented.
arm/marvell/armada-cpu-reset.txt has generic name and describes only one
reset controller (370) while being used on multiple SoC (370, 375, 38x,
39x). I could go like this all over the bindings...
Best regards,
Krzysztof
@@ -1,21 +0,0 @@-Device Tree bindings for MVEBU SDRAM controllers--The Marvell EBU SoCs all have a SDRAM controller. The SDRAM controller-differs from one SoC variant to another, but they also share a number-of commonalities.--For now, this Device Tree binding documentation only documents the-Armada XP SDRAM controller.
Please keep the description, otherwise it would be confusing why the binding is
named marvell,mvebu-sdram-controller.yaml although it (currenly) only applies to
the Armada XP.
The description does not explain why it only documents Armada XP, so it
just duplicates what is in "compatible" part of bindings. How is the
confusion removed by saying "we document currently only Armada XP"? What
changes?
Then perhaps the binding should be named marvell,armada-xp-sdram-
controller.yaml? It find it unlikely that support for the other SoC's
controllers will be added, given their age.
Sure, could be like this but there is no confusion here and no need to
fix anything. It is understandable and common to name bindings file as
general (e.g. for group of devices) even though only limited amount of
devices are currently documented/described. It's almost everywhere like
this, when the bindings are not complete. I don't see where is the
confusion.
Look at: arm/marvell/armada-cpu-reset.txt which mentions several SoCs
while only three compatibles are documented.
arm/marvell/armada-cpu-reset.txt has generic name and describes only one
reset controller (370) while being used on multiple SoC (370, 375, 38x,
39x). I could go like this all over the bindings...
OK, you convinced me. Thanks for the explanation.
Jan
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