[PATCH V1] arm64: dts: qcom: sc7180: Use maximum drive strength values for eMMC

The current drive strength values are not sufficient on non discrete
boards and this leads to CRC errors during switching to HS400 enhanced
strobe mode.

Hardware simulation results on non discrete boards shows up that use the
maximum drive strength values for data and command lines could helps
in avoiding these CRC errors.

So, update data and command line drive strength values to maximum.

Signed-off-by: Shaik Sajida Bhanu <redacted>
---
 arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi
index 0f2b3c0..79d7aa6 100644
--- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi

@@ -1524,13 +1524,13 @@ ap_spi_fp: &spi10 {
 		pinconf-cmd {
 			pins = "sdc1_cmd";
 			bias-pull-up;
-			drive-strength = <10>;
+			drive-strength = <16>;
 		};
 
 		pinconf-data {
 			pins = "sdc1_data";
 			bias-pull-up;
-			drive-strength = <10>;
+			drive-strength = <16>;
 		};
 
 		pinconf-rclk {

-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member 
of Code Aurora Forum, hosted by The Linux Foundation

Hi,

On Mon, Aug 16, 2021 at 9:51 AM Shaik Sajida Bhanu
[off-list ref] wrote:

The current drive strength values are not sufficient on non discrete
boards and this leads to CRC errors during switching to HS400 enhanced
strobe mode.

Hardware simulation results on non discrete boards shows up that use the
maximum drive strength values for data and command lines could helps
in avoiding these CRC errors.

So, update data and command line drive strength values to maximum.

Signed-off-by: Shaik Sajida Bhanu <redacted>
---
 arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

I found this CL because you created a bug for it (thanks!), but it
would have also been nice if you had CCed some folks from Google that
work on the trogdor project on your patch.

I could be convinced that this is the right thing to do, but I want to
really make sure that it has had sufficient testing. Specifically as
this patch is written we'll be updating the drive strength for all
boards. Increasing the drive strength can sometimes introduce new
problems (reflections, noise, ...) so we have to be confident that
we're not breaking someone that used to work by increasing the drive
strength here. How much has this been tested?

From the discussions in the bugs, it seemed like the increased drive
strength was only needed for one eMMC part and that eMMC part still
had problems even after the increased drive strength, it just had
fewer problems. It would be good to confirm that I got my data
straight, but if it's right I'd be inclined _not_ to increase the
drive strength and simply to make sure we don't use that eMMC part (or
solve the problems with it in a different way). I seem to remember
that there were other eMMC-related values that could be set. Any
chance the problems are really there? Like `fixed-emmc-driver-type`?

-Doug

Hi,

On Tue, Aug 17, 2021 at 6:58 AM Doug Anderson [off-list ref] wrote:

quoted

                pinconf-data {
                        pins = "sdc1_data";
                        bias-pull-up;
-                       drive-strength = <10>;
+                       drive-strength = <16>;

I could be convinced that this is the right thing to do, but I want to
really make sure that it has had sufficient testing. Specifically as
this patch is written we'll be updating the drive strength for all
boards. Increasing the drive strength can sometimes introduce new
problems (reflections, noise, ...) so we have to be confident that
we're not breaking someone that used to work by increasing the drive
strength here. How much has this been tested?

From further discussion internally, it sounds as if this should be
fine and fixes more than just this one eMMC part. Thus:

Reviewed-by: Douglas Anderson <dianders@chromium.org>

Bjorn,

On Thu, Aug 19, 2021 at 6:44 AM Doug Anderson [off-list ref] wrote:

Hi,

On Tue, Aug 17, 2021 at 6:58 AM Doug Anderson [off-list ref] wrote:

quoted

quoted

                pinconf-data {
                        pins = "sdc1_data";
                        bias-pull-up;
-                       drive-strength = <10>;
+                       drive-strength = <16>;

I could be convinced that this is the right thing to do, but I want to
really make sure that it has had sufficient testing. Specifically as
this patch is written we'll be updating the drive strength for all
boards. Increasing the drive strength can sometimes introduce new
problems (reflections, noise, ...) so we have to be confident that
we're not breaking someone that used to work by increasing the drive
strength here. How much has this been tested?

From further discussion internally, it sounds as if this should be
fine and fixes more than just this one eMMC part. Thus:

Reviewed-by: Douglas Anderson <dianders@chromium.org>

We've been running with this patch in the Chrome OS kernel. If it
looks OK to you, it'd be great for it to land in your tree. Thanks!

-Doug

On Mon, 16 Aug 2021 22:20:50 +0530, Shaik Sajida Bhanu wrote:

The current drive strength values are not sufficient on non discrete
boards and this leads to CRC errors during switching to HS400 enhanced
strobe mode.

Hardware simulation results on non discrete boards shows up that use the
maximum drive strength values for data and command lines could helps
in avoiding these CRC errors.

[...]

Applied, thanks!

[1/1] arm64: dts: qcom: sc7180: Use maximum drive strength values for eMMC
      commit: 752432e40e8f0d02d0af07cce2d6d4b250be11ef

Best regards,
-- 
Bjorn Andersson [off-list ref]