[PATCH] arm64: dts: exynos: correct GIC CPU interfaces address range on Exynos7

Subsystems: arm/samsung s3c, s5p and exynos arm architectures, the rest

STALE1891d LANDED

Landed in mainline as 01c72cad790c on 2021-08-09.

8 messages, 3 authors, 2021-08-09 · open the first message on its own page

[PATCH] arm64: dts: exynos: correct GIC CPU interfaces address range on Exynos7

From: Krzysztof Kozlowski <hidden>
Date: 2021-08-05 07:23:01

The GIC-400 CPU interfaces address range is defined as 0x2000-0x3FFF (by
ARM).

Reported-by: Sam Protsenko <semen.protsenko@linaro.org>
Reported-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Krzysztof Kozlowski <redacted>
---
 arch/arm64/boot/dts/exynos/exynos7.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi b/arch/arm64/boot/dts/exynos/exynos7.dtsi
index 8b06397ba6e7..c73a597ca66e 100644
--- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi

@@ -137,7 +137,7 @@ gic: interrupt-controller@11001000 {
 			#address-cells = <0>;
 			interrupt-controller;
 			reg =	<0x11001000 0x1000>,
-				<0x11002000 0x1000>,
+				<0x11002000 0x2000>,
 				<0x11004000 0x2000>,
 				<0x11006000 0x2000>;
 		};

-- 
2.30.2

Re: [PATCH] arm64: dts: exynos: correct GIC CPU interfaces address range on Exynos7

From: Krzysztof Kozlowski <hidden>
Date: 2021-08-05 07:36:55

On 05/08/2021 09:21, Krzysztof Kozlowski wrote:

The GIC-400 CPU interfaces address range is defined as 0x2000-0x3FFF (by
ARM).

I underestimated the issue - this is actually bug as there is a GICC_DIR
register at offset 0x1000. Therefore:

Fixes: b9024cbc937d ("arm64: dts: Add initial device tree support for exynos7")

quoted hunk

Reported-by: Sam Protsenko <semen.protsenko@linaro.org>
Reported-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Krzysztof Kozlowski <redacted>
---
 arch/arm64/boot/dts/exynos/exynos7.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi b/arch/arm64/boot/dts/exynos/exynos7.dtsi
index 8b06397ba6e7..c73a597ca66e 100644
--- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi

@@ -137,7 +137,7 @@ gic: interrupt-controller@11001000 {
 			#address-cells = <0>;
 			interrupt-controller;
 			reg =	<0x11001000 0x1000>,
-				<0x11002000 0x1000>,
+				<0x11002000 0x2000>,
 				<0x11004000 0x2000>,
 				<0x11006000 0x2000>;
 		};


Best regards,
Krzysztof

RE: [PATCH] arm64: dts: exynos: correct GIC CPU interfaces address range on Exynos7

From: "Alim Akhtar" <alim.akhtar@samsung.com>
Date: 2021-08-05 09:32:39

Hi Krzysztof,

-----Original Message-----
From: Krzysztof Kozlowski <redacted>
Sent: 05 August 2021 13:07
To: Rob Herring <robh+dt@kernel.org>; devicetree@vger.kernel.org; linux-
arm-kernel@lists.infradead.org; linux-samsung-soc@vger.kernel.org; linux-
kernel@vger.kernel.org
Cc: Alim Akhtar <alim.akhtar@samsung.com>; Chanwoo Choi
[off-list ref]; Pankaj Dubey [off-list ref];
Sam Protsenko [off-list ref]; Marc Zyngier
[off-list ref]
Subject: Re: [PATCH] arm64: dts: exynos: correct GIC CPU interfaces address
range on Exynos7

On 05/08/2021 09:21, Krzysztof Kozlowski wrote:

quoted

The GIC-400 CPU interfaces address range is defined as 0x2000-0x3FFF
(by ARM).

Looking at DDI0471B_gic400_r0p1_trm.pdf, CPU interface range is 0x0000 ~ 0x10000

I underestimated the issue - this is actually bug as there is a GICC_DIR
register at offset 0x1000. Therefore:

Looking at the exynos7 and exynos5433 UMs looks like GICC_DIR is at offset 0x2100 (from 0x1100_0000 GIC base)
It is possible for you to cross check once?

Fixes: b9024cbc937d ("arm64: dts: Add initial device tree support for
exynos7")

quoted

Reported-by: Sam Protsenko <semen.protsenko@linaro.org>
Reported-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Krzysztof Kozlowski <redacted>
---
 arch/arm64/boot/dts/exynos/exynos7.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi

b/arch/arm64/boot/dts/exynos/exynos7.dtsi
index 8b06397ba6e7..c73a597ca66e 100644

--- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi

@@ -137,7 +137,7 @@ gic: interrupt-controller@11001000 {
 			#address-cells = <0>;
 			interrupt-controller;
 			reg =	<0x11001000 0x1000>,
-				<0x11002000 0x1000>,
+				<0x11002000 0x2000>,
 				<0x11004000 0x2000>,
 				<0x11006000 0x2000>;
 		};


Best regards,
Krzysztof

Re: [PATCH] arm64: dts: exynos: correct GIC CPU interfaces address range on Exynos7

From: Krzysztof Kozlowski <hidden>
Date: 2021-08-05 09:43:45

On 05/08/2021 11:26, Alim Akhtar wrote:

Hi Krzysztof,

quoted

-----Original Message-----
From: Krzysztof Kozlowski <redacted>
Sent: 05 August 2021 13:07
To: Rob Herring <robh+dt@kernel.org>; devicetree@vger.kernel.org; linux-
arm-kernel@lists.infradead.org; linux-samsung-soc@vger.kernel.org; linux-
kernel@vger.kernel.org
Cc: Alim Akhtar <alim.akhtar@samsung.com>; Chanwoo Choi
[off-list ref]; Pankaj Dubey [off-list ref];
Sam Protsenko [off-list ref]; Marc Zyngier
[off-list ref]
Subject: Re: [PATCH] arm64: dts: exynos: correct GIC CPU interfaces address
range on Exynos7

On 05/08/2021 09:21, Krzysztof Kozlowski wrote:

quoted

The GIC-400 CPU interfaces address range is defined as 0x2000-0x3FFF
(by ARM).

Looking at DDI0471B_gic400_r0p1_trm.pdf, CPU interface range is 0x0000 ~ 0x10000

quoted

I underestimated the issue - this is actually bug as there is a GICC_DIR
register at offset 0x1000. Therefore:

Looking at the exynos7 and exynos5433 UMs looks like GICC_DIR is at offset 0x2100 (from 0x1100_0000 GIC base)
It is possible for you to cross check once?

That's a mistake in Exynos manual. GICC_DIR is at 0x1000:
https://developer.arm.com/documentation/ddi0471/b/programmers-model/cpu-interface-register-summary

We have discussion here:
https://lore.kernel.org/linux-samsung-soc/0277c701-cc25-cdc5-d3b9-cf2cc2ba4de5@canonical.com/T/#m1ced9a28bed27f5cf74e281fb68efe1b57d5609e

Range of 0x10000 is definitely wrong as it overlaps with two other
ranges.


Best regards,
Krzysztof

Re: [PATCH] arm64: dts: exynos: correct GIC CPU interfaces address range on Exynos7

From: Krzysztof Kozlowski <hidden>
Date: 2021-08-05 09:45:31

On 05/08/2021 11:43, Krzysztof Kozlowski wrote:

On 05/08/2021 11:26, Alim Akhtar wrote:

quoted

Hi Krzysztof,

quoted

-----Original Message-----
From: Krzysztof Kozlowski <redacted>
Sent: 05 August 2021 13:07
To: Rob Herring <robh+dt@kernel.org>; devicetree@vger.kernel.org; linux-
arm-kernel@lists.infradead.org; linux-samsung-soc@vger.kernel.org; linux-
kernel@vger.kernel.org
Cc: Alim Akhtar <alim.akhtar@samsung.com>; Chanwoo Choi
[off-list ref]; Pankaj Dubey [off-list ref];
Sam Protsenko [off-list ref]; Marc Zyngier
[off-list ref]
Subject: Re: [PATCH] arm64: dts: exynos: correct GIC CPU interfaces address
range on Exynos7

On 05/08/2021 09:21, Krzysztof Kozlowski wrote:

quoted

The GIC-400 CPU interfaces address range is defined as 0x2000-0x3FFF
(by ARM).

Looking at DDI0471B_gic400_r0p1_trm.pdf, CPU interface range is 0x0000 ~ 0x10000

quoted

I underestimated the issue - this is actually bug as there is a GICC_DIR
register at offset 0x1000. Therefore:

Looking at the exynos7 and exynos5433 UMs looks like GICC_DIR is at offset 0x2100 (from 0x1100_0000 GIC base)
It is possible for you to cross check once?

That's a mistake in Exynos manual. GICC_DIR is at 0x1000:

0x1000 from CPU base offset, so 0x3000 from GIC base.

https://developer.arm.com/documentation/ddi0471/b/programmers-model/cpu-interface-register-summary

We have discussion here:
https://lore.kernel.org/linux-samsung-soc/0277c701-cc25-cdc5-d3b9-cf2cc2ba4de5@canonical.com/T/#m1ced9a28bed27f5cf74e281fb68efe1b57d5609e

Range of 0x10000 is definitely wrong as it overlaps with two other
ranges.


Best regards,
Krzysztof

RE: [PATCH] arm64: dts: exynos: correct GIC CPU interfaces address range on Exynos7

From: "Alim Akhtar" <alim.akhtar@samsung.com>
Date: 2021-08-05 09:59:52

-----Original Message-----
From: Krzysztof Kozlowski <redacted>
Sent: 05 August 2021 15:15
To: Alim Akhtar <alim.akhtar@samsung.com>; 'Rob Herring'
[off-list ref]; devicetree@vger.kernel.org; linux-arm-
kernel@lists.infradead.org; linux-samsung-soc@vger.kernel.org; linux-
kernel@vger.kernel.org
Cc: 'Chanwoo Choi' <cw00.choi@samsung.com>; 'Pankaj Dubey'
[off-list ref]; 'Sam Protsenko'
[off-list ref]; 'Marc Zyngier' [off-list ref]
Subject: Re: [PATCH] arm64: dts: exynos: correct GIC CPU interfaces address
range on Exynos7

On 05/08/2021 11:43, Krzysztof Kozlowski wrote:

quoted

On 05/08/2021 11:26, Alim Akhtar wrote:

quoted

Hi Krzysztof,

quoted

-----Original Message-----
From: Krzysztof Kozlowski <redacted>
Sent: 05 August 2021 13:07
To: Rob Herring <robh+dt@kernel.org>; devicetree@vger.kernel.org;
linux- arm-kernel@lists.infradead.org;
linux-samsung-soc@vger.kernel.org; linux- kernel@vger.kernel.org
Cc: Alim Akhtar <alim.akhtar@samsung.com>; Chanwoo Choi
[off-list ref]; Pankaj Dubey

[off-list ref];

quoted

Sam Protsenko [off-list ref]; Marc Zyngier
[off-list ref]
Subject: Re: [PATCH] arm64: dts: exynos: correct GIC CPU interfaces
address range on Exynos7

On 05/08/2021 09:21, Krzysztof Kozlowski wrote:

quoted

The GIC-400 CPU interfaces address range is defined as
0x2000-0x3FFF (by ARM).

Looking at DDI0471B_gic400_r0p1_trm.pdf, CPU interface range is
0x0000 ~ 0x10000

quoted

I underestimated the issue - this is actually bug as there is a
GICC_DIR register at offset 0x1000. Therefore:

Looking at the exynos7 and exynos5433 UMs looks like GICC_DIR is at
offset 0x2100 (from 0x1100_0000 GIC base) It is possible for you to cross

check once?

quoted

That's a mistake in Exynos manual. GICC_DIR is at 0x1000:

0x1000 from CPU base offset, so 0x3000 from GIC base.

quoted

https://developer.arm.com/documentation/ddi0471/b/programmers-

model/cp

quoted

u-interface-register-summary

We have discussion here:
https://lore.kernel.org/linux-samsung-soc/0277c701-cc25-cdc5-d3b9-cf2c

c2ba4de5@canonical.com/T/#m1ced9a28bed27f5cf74e281fb68efe1b57d5609
e

Thanks for pointing to this discussion, I missed this.
Agreed.
Feel Free to add
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>

quoted

Range of 0x10000 is definitely wrong as it overlaps with two other
ranges.


Best regards,
Krzysztof

Re: [PATCH] arm64: dts: exynos: correct GIC CPU interfaces address range on Exynos7

From: Sam Protsenko <semen.protsenko@linaro.org>
Date: 2021-08-05 11:26:54

Hi Krzysztof,

On Thu, 5 Aug 2021 at 10:22, Krzysztof Kozlowski
[off-list ref] wrote:

The GIC-400 CPU interfaces address range is defined as 0x2000-0x3FFF (by
ARM).

Reported-by: Sam Protsenko <semen.protsenko@linaro.org>
Reported-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Krzysztof Kozlowski <redacted>
---

Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>

quoted hunk

 arch/arm64/boot/dts/exynos/exynos7.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi b/arch/arm64/boot/dts/exynos/exynos7.dtsi
index 8b06397ba6e7..c73a597ca66e 100644
--- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi

@@ -137,7 +137,7 @@ gic: interrupt-controller@11001000 {
                        #address-cells = <0>;
                        interrupt-controller;
                        reg =   <0x11001000 0x1000>,
-                               <0x11002000 0x1000>,
+                               <0x11002000 0x2000>,
                                <0x11004000 0x2000>,
                                <0x11006000 0x2000>;
                };
--

2.30.2

Re: [PATCH] arm64: dts: exynos: correct GIC CPU interfaces address range on Exynos7

From: Krzysztof Kozlowski <hidden>
Date: 2021-08-09 10:40:12

On Thu, 5 Aug 2021 09:21:10 +0200, Krzysztof Kozlowski wrote:

The GIC-400 CPU interfaces address range is defined as 0x2000-0x3FFF (by
ARM).

Applied, thanks!

[1/1] arm64: dts: exynos: correct GIC CPU interfaces address range on Exynos7
      commit: 01c72cad790cb6cd3ccbe4c1402b6cb6c6bbffd0

Best regards,
-- 
Krzysztof Kozlowski [off-list ref]

`h`	back out one level
`j`	next message in thread
`k`	previous message in thread
`l`	drill in
`Esc`	close help / fold thread tree
`?`	toggle this help