[PATCH v2 0/3] nvmem: qfprom: Add binding updates and power-domain handling

v2:
* pm_runtime calls made unconditionally, should work even without the power-domains property in DT
* Added the missing pm_runtime_disable() handling
* DT patch rebased on msm/for-next

--
qfprom devices on sc7280 have an additional requirement to vote on a power-domain
performance state to reliably blow fuses. Add the binding updates and handle this in
the driver, also add the DT node for sc7280 platform.

Rajendra Nayak (3):
  dt-bindings: nvmem: qfprom: Add optional power-domains property
  nvmem: qfprom: sc7280: Handle the additional power-domains vote
  arm64: dts: qcom: sc7280: Add qfprom node

 .../devicetree/bindings/nvmem/qcom,qfprom.yaml     |  3 +++
 arch/arm64/boot/dts/qcom/sc7280.dtsi               | 13 +++++++++++
 drivers/nvmem/qfprom.c                             | 26 ++++++++++++++++++++++
 3 files changed, 42 insertions(+)

-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

qfprom devices on some SoCs need to vote on the performance state
of a power-domain, so add the power-domains optional property to the
bindings

Signed-off-by: Rajendra Nayak <redacted>
---
 Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml b/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml
index 861b205..a498a08 100644
--- a/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml
+++ b/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml

@@ -51,6 +51,9 @@ properties:
   vcc-supply:
     description: Our power supply.
 
+  power-domains:
+    description: A phandle to a power domain node.
+
   # Needed if any child nodes are present.
   "#address-cells":
     const: 1

-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

Hi,

On Thu, Jul 29, 2021 at 5:01 AM Rajendra Nayak [off-list ref] wrote:

I'm trying to channel my inner Rob here by saying that this
description doesn't add anything and this should just be:

power-domains:
  maxItems: 1

Here's an example of Rob saying this:

https://lore.kernel.org/linux-devicetree/20210712151322.GA1931925@robh.at.kernel.org/

Other than that, feel free to add my "Reviewed-by" tag.

-Doug

On 7/29/2021 9:49 PM, Doug Anderson wrote:

Hi,

On Thu, Jul 29, 2021 at 5:01 AM Rajendra Nayak [off-list ref] wrote:

quoted

qfprom devices on some SoCs need to vote on the performance state
of a power-domain, so add the power-domains optional property to the
bindings

Signed-off-by: Rajendra Nayak <redacted>
---
  Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml | 3 +++
  1 file changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml b/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml
index 861b205..a498a08 100644
--- a/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml
+++ b/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml

@@ -51,6 +51,9 @@ properties:
    vcc-supply:
      description: Our power supply.

+  power-domains:
+    description: A phandle to a power domain node.
+

I'm trying to channel my inner Rob here by saying that this
description doesn't add anything and this should just be:

Thanks, I trust the inner Rob in you :), so I'll drop the description
and repost.

power-domains:
   maxItems: 1

Here's an example of Rob saying this:

https://lore.kernel.org/linux-devicetree/20210712151322.GA1931925@robh.at.kernel.org/

Other than that, feel free to add my "Reviewed-by" tag.

-Doug

-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

Add the qfprom node and its properties for the sc7280 SoC.

Signed-off-by: Rajendra Nayak <redacted>
---
 arch/arm64/boot/dts/qcom/sc7280.dtsi | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 029723a..e87b210 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi

@@ -442,6 +442,19 @@
 			#mbox-cells = <2>;
 		};
 
+		qfprom: efuse@784000 {
+			compatible = "qcom,sc7280-qfprom", "qcom,qfprom";
+			reg = <0 0x00784000 0 0xa20>,
+			      <0 0x00780000 0 0xa20>,
+			      <0 0x00782000 0 0x120>,
+			      <0 0x00786000 0 0x1fff>;
+			clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>;
+			clock-names = "core";
+			power-domains = <&rpmhpd SC7280_MX>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+		};
+
 		sdhc_1: sdhci@7c4000 {
 			compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5";
 			status = "disabled";

-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

Hi,

On Thu, Jul 29, 2021 at 5:01 AM Rajendra Nayak [off-list ref] wrote:

Add the qfprom node and its properties for the sc7280 SoC.

Signed-off-by: Rajendra Nayak <redacted>
---
 arch/arm64/boot/dts/qcom/sc7280.dtsi | 13 +++++++++++++
 1 file changed, 13 insertions(+)

Peachy! I guess a future patch will add things like USB2 trim and GPU
speed bin definitions?

Reviewed-by: Douglas Anderson <dianders@chromium.org>

On 7/29/2021 9:54 PM, Doug Anderson wrote:

Hi,

On Thu, Jul 29, 2021 at 5:01 AM Rajendra Nayak [off-list ref] wrote:

quoted

Add the qfprom node and its properties for the sc7280 SoC.

Signed-off-by: Rajendra Nayak <redacted>
---
  arch/arm64/boot/dts/qcom/sc7280.dtsi | 13 +++++++++++++
  1 file changed, 13 insertions(+)

Peachy! I guess a future patch will add things like USB2 trim and GPU
speed bin definitions?

Right, I left those out for a future patch.

Reviewed-by: Douglas Anderson <dianders@chromium.org>

Thanks

-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

On sc7280, to reliably blow fuses, we need an additional vote
on max performance state of 'MX' power-domain.
Add support for power-domain performance state voting in the
driver.

Signed-off-by: Rajendra Nayak <redacted>
---
 drivers/nvmem/qfprom.c | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/drivers/nvmem/qfprom.c b/drivers/nvmem/qfprom.c
index 81fbad5..b5f27df 100644
--- a/drivers/nvmem/qfprom.c
+++ b/drivers/nvmem/qfprom.c

@@ -12,6 +12,8 @@
 #include <linux/mod_devicetable.h>
 #include <linux/nvmem-provider.h>
 #include <linux/platform_device.h>
+#include <linux/pm_domain.h>
+#include <linux/pm_runtime.h>
 #include <linux/property.h>
 #include <linux/regulator/consumer.h>
 

@@ -139,6 +141,9 @@ static void qfprom_disable_fuse_blowing(const struct qfprom_priv *priv,
 {
 	int ret;
 
+	dev_pm_genpd_set_performance_state(priv->dev, 0);
+	pm_runtime_put(priv->dev);
+
 	/*
 	 * This may be a shared rail and may be able to run at a lower rate
 	 * when we're not blowing fuses.  At the moment, the regulator framework

@@ -212,6 +217,14 @@ static int qfprom_enable_fuse_blowing(const struct qfprom_priv *priv,
 		goto err_clk_rate_set;
 	}
 
+	ret = pm_runtime_get_sync(priv->dev);
+	if (ret < 0) {
+		pm_runtime_put_noidle(priv->dev);
+		dev_err(priv->dev, "Failed to enable power-domain\n");
+		goto err_reg_enable;
+	}
+	dev_pm_genpd_set_performance_state(priv->dev, INT_MAX);
+
 	old->timer_val = readl(priv->qfpconf + QFPROM_BLOW_TIMER_OFFSET);
 	old->accel_val = readl(priv->qfpconf + QFPROM_ACCEL_OFFSET);
 	writel(priv->soc_data->qfprom_blow_timer_value,

@@ -221,6 +234,8 @@ static int qfprom_enable_fuse_blowing(const struct qfprom_priv *priv,
 
 	return 0;
 
+err_reg_enable:
+	regulator_disable(priv->vcc);
 err_clk_rate_set:
 	clk_set_rate(priv->secclk, old->clk_rate);
 err_clk_prepared:

@@ -320,6 +335,11 @@ static int qfprom_reg_read(void *context,
 	return 0;
 }
 
+static void qfprom_runtime_disable(void *data)
+{
+	pm_runtime_disable(data);
+}
+
 static const struct qfprom_soc_data qfprom_7_8_data = {
 	.accel_value = 0xD10,
 	.qfprom_blow_timer_value = 25,

@@ -420,6 +440,12 @@ static int qfprom_probe(struct platform_device *pdev)
 			econfig.reg_write = qfprom_reg_write;
 	}
 
+	ret = devm_add_action_or_reset(dev, qfprom_runtime_disable, dev);
+	if (ret)
+		return ret;
+
+	pm_runtime_enable(dev);
+
 	nvmem = devm_nvmem_register(dev, &econfig);
 
 	return PTR_ERR_OR_ZERO(nvmem);

-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

Hi,

On Thu, Jul 29, 2021 at 5:01 AM Rajendra Nayak [off-list ref] wrote:

To me it feels as if this should be at the end of the function rather
than the beginning. I guess it doesn't matter (?), but it feels wrong
that we have writes to the register space after we're don't a
pm_runtime_put().

Swap the order of the two. IOW first pm_runtime_enable(), then
devm_add_action_or_reset(). Specifically the "_or_reset" means that if
you fail to add the action (AKA devm_add_action() fails to allocate
the tiny amount of memory it needs) it will actually _call_ the
action. That means that in your code if the memory allocation fails
you'll call pm_runtime_disable() without the corresponding
pm_runtime_enable().


Other than those two issues this looks good to me. Feel free to add my
Reviewed-by when you fix them.

-Doug

On 7/29/2021 9:37 PM, Doug Anderson wrote:

Hi,

On Thu, Jul 29, 2021 at 5:01 AM Rajendra Nayak [off-list ref] wrote:

quoted

On sc7280, to reliably blow fuses, we need an additional vote
on max performance state of 'MX' power-domain.
Add support for power-domain performance state voting in the
driver.

Signed-off-by: Rajendra Nayak <redacted>
---
  drivers/nvmem/qfprom.c | 26 ++++++++++++++++++++++++++
  1 file changed, 26 insertions(+)

diff --git a/drivers/nvmem/qfprom.c b/drivers/nvmem/qfprom.c
index 81fbad5..b5f27df 100644
--- a/drivers/nvmem/qfprom.c
+++ b/drivers/nvmem/qfprom.c

@@ -12,6 +12,8 @@
  #include <linux/mod_devicetable.h>
  #include <linux/nvmem-provider.h>
  #include <linux/platform_device.h>
+#include <linux/pm_domain.h>
+#include <linux/pm_runtime.h>
  #include <linux/property.h>
  #include <linux/regulator/consumer.h>

@@ -139,6 +141,9 @@ static void qfprom_disable_fuse_blowing(const struct qfprom_priv *priv,
  {
         int ret;

+       dev_pm_genpd_set_performance_state(priv->dev, 0);
+       pm_runtime_put(priv->dev);

To me it feels as if this should be at the end of the function rather
than the beginning. I guess it doesn't matter (?), but it feels wrong
that we have writes to the register space after we're don't a
pm_runtime_put().

Right, I was confused with this too when I saw that the other resources
(regulator/clocks) were also turned off before we write into the
register space. And then looking into the driver I realized its perhaps because
the resources are needed only for the 'raw' writes and the 'conf'
read/writes can happen regardless. I'll just fix that up and put the register
writes before we really turn off any resources to avoid confusion.

quoted

@@ -420,6 +440,12 @@ static int qfprom_probe(struct platform_device *pdev)
                         econfig.reg_write = qfprom_reg_write;
         }

+       ret = devm_add_action_or_reset(dev, qfprom_runtime_disable, dev);
+       if (ret)
+               return ret;
+
+       pm_runtime_enable(dev);
+

Swap the order of the two. IOW first pm_runtime_enable(), then
devm_add_action_or_reset(). Specifically the "_or_reset" means that if
you fail to add the action (AKA devm_add_action() fails to allocate
the tiny amount of memory it needs) it will actually _call_ the
action. 

Ah, I didn't know that, thanks, I'll fix the order up and repost.

That means that in your code if the memory allocation fails
you'll call pm_runtime_disable() without the corresponding
pm_runtime_enable().


Other than those two issues this looks good to me. Feel free to add my
Reviewed-by when you fix them.

Thanks.

-Doug

-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation