Re: [PATCH v2 2/2] net: stmmac: Add Ingenic SoCs MAC support.

Here is Ingenic's reply, the time length corresponding to a unit is 19.5ps
(19500fs).

Sometimes, there is a negative offset in the delays. So a delay value
of 0 written to the register actually means -200ps or something.

   Andrew

于 Thu, 10 Jun 2021 16:57:29 +0200
Andrew Lunn [off-list ref] 写道:

quoted

Here is Ingenic's reply, the time length corresponding to a unit is
19.5ps (19500fs).  

Sometimes, there is a negative offset in the delays. So a delay value
of 0 written to the register actually means -200ps or something.

Ah, perhaps this explains why we still need to add fine-tuning
parameter in rgmii-id and rgmii-txid modes to ensure that the network
works properly.

   Andrew

On Sun, Jun 13, 2021 at 04:34:52PM +0800, 周琰杰 wrote:

于 Thu, 10 Jun 2021 16:57:29 +0200
Andrew Lunn [off-list ref] 写道:

quoted

quoted

Here is Ingenic's reply, the time length corresponding to a unit is
19.5ps (19500fs).  

Sometimes, there is a negative offset in the delays. So a delay value
of 0 written to the register actually means -200ps or something.

Ah, perhaps this explains why we still need to add fine-tuning
parameter in rgmii-id and rgmii-txid modes to ensure that the network
works properly.

Please try to find this out. rgmii means no delay. If the hardware is
doing -500pS by default, you need to take this into account, and add
the 500pS back on.

    Andrew

Hi Andrew,

于 Sun, 13 Jun 2021 18:31:36 +0200
Andrew Lunn [off-list ref] 写道:

On Sun, Jun 13, 2021 at 04:34:52PM +0800, 周琰杰 wrote:

quoted

于 Thu, 10 Jun 2021 16:57:29 +0200
Andrew Lunn [off-list ref] 写道:
  

quoted

quoted

Here is Ingenic's reply, the time length corresponding to a
unit is 19.5ps (19500fs).    

Sometimes, there is a negative offset in the delays. So a delay
value of 0 written to the register actually means -200ps or
something.  

Ah, perhaps this explains why we still need to add fine-tuning
parameter in rgmii-id and rgmii-txid modes to ensure that the
network works properly.  

Please try to find this out. rgmii means no delay. If the hardware is
doing -500pS by default, you need to take this into account, and add
the 500pS back on.

I think I may have found the problem. At present, my PHY uses a
general driver, and there is no specific setting for delay-related
registers. The default delay value of PHY is 1ns, which does not meet
the delay requirement of 2ns, after and the MAC side add 500ps delay
(and possibly some delays introduced on the hardware circuit), it just
meets the requirement of 2ns delay.

    Andrew