# Re: \[PATCH RESEND v2 2/6\] dt-bindings: phy: mediatek,mt7621-pci-phy: add clock entries

- From: Rob Herring \<robh@kernel.org\>
- Date: 2021-05-10 16:01:55 
- List: linux-devicetree
- Page: https://ratatoskr.run/linux-devicetree/2021/05/8191002
- Thread: https://ratatoskr.run/linux-phy/2021/05/8190944/t.md

```text
On Sat, 08 May 2021 09:09:26 +0200, Sergio Paracuellos wrote:
> MT7621 SoC clock driver has already mainlined in
> 'commit 48df7a26f470 ("clk: ralink: add clock driver for mt7621 SoC")'
> Hence update schema with the add of the entries related to
> clock. Since until now things were not properly being done
> we mark also 'clock' as required in the binding since this
> will be now the only way to properly retrieve frequency to be
> able to make a correct configuration of the PCIe phy registers.
> 
> Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
> ---
>  .../devicetree/bindings/phy/mediatek,mt7621-pci-phy.yaml     | 5 +++++
>  1 file changed, 5 insertions(+)
> 

Acked-by: Rob Herring <robh@kernel.org>
```