This series implements mitigations for lack of DMA access control on
systems without an IOMMU, which could result in the DMA accessing the
system memory at unexpected times and/or unexpected addresses, possibly
leading to data leakage or corruption.
For example, we plan to use the PCI-e bus for Wi-Fi and that PCI-e bus is
not behind an IOMMU. As PCI-e, by design, gives the device full access to
system memory, a vulnerability in the Wi-Fi firmware could easily escalate
to a full system exploit (remote wifi exploits: [1a], [1b] that shows a
full chain of exploits; [2], [3]).
To mitigate the security concerns, we introduce restricted DMA. Restricted
DMA utilizes the existing swiotlb to bounce streaming DMA in and out of a
specially allocated region and does memory allocation from the same region.
The feature on its own provides a basic level of protection against the DMA
overwriting buffer contents at unexpected times. However, to protect
against general data leakage and system memory corruption, the system needs
to provide a way to restrict the DMA to a predefined memory region (this is
usually done at firmware level, e.g. MPU in ATF on some ARM platforms [4]).
[1a] https://googleprojectzero.blogspot.com/2017/04/over-air-exploiting-broadcoms-wi-fi_4.html
[1b] https://googleprojectzero.blogspot.com/2017/04/over-air-exploiting-broadcoms-wi-fi_11.html
[2] https://blade.tencent.com/en/advisories/qualpwn/
[3] https://www.bleepingcomputer.com/news/security/vulnerabilities-found-in-highly-popular-firmware-for-wifi-chips/
[4] https://github.com/ARM-software/arm-trusted-firmware/blob/master/plat/mediatek/mt8183/drivers/emi_mpu/emi_mpu.c#L132
Claire Chang (14):
swiotlb: Remove external access to io_tlb_start
swiotlb: Move is_swiotlb_buffer() to swiotlb.c
swiotlb: Add struct swiotlb
swiotlb: Refactor swiotlb_late_init_with_tbl
swiotlb: Add DMA_RESTRICTED_POOL
swiotlb: Add restricted DMA pool
swiotlb: Update swiotlb API to gain a struct device argument
swiotlb: Use restricted DMA pool if available
swiotlb: Refactor swiotlb_tbl_{map,unmap}_single
dma-direct: Add a new wrapper __dma_direct_free_pages()
swiotlb: Add is_dev_swiotlb_force()
swiotlb: Add restricted DMA alloc/free support.
dt-bindings: of: Add restricted DMA pool
of: Add plumbing for restricted DMA pool
.../reserved-memory/reserved-memory.txt | 24 +
arch/powerpc/platforms/pseries/svm.c | 4 +-
drivers/iommu/dma-iommu.c | 12 +-
drivers/of/address.c | 25 +
drivers/of/device.c | 3 +
drivers/of/of_private.h | 5 +
drivers/xen/swiotlb-xen.c | 4 +-
include/linux/device.h | 4 +
include/linux/swiotlb.h | 32 +-
kernel/dma/Kconfig | 14 +
kernel/dma/direct.c | 51 +-
kernel/dma/direct.h | 8 +-
kernel/dma/swiotlb.c | 636 ++++++++++++------
13 files changed, 582 insertions(+), 240 deletions(-)
--
v4:
- Fix spinlock bad magic
- Use rmem->name for debugfs entry
- Address the comments in v3
v3:
Using only one reserved memory region for both streaming DMA and memory
allocation.
https://lore.kernel.org/patchwork/cover/1360992/
v2:
Building on top of swiotlb.
https://lore.kernel.org/patchwork/cover/1280705/
v1:
Using dma_map_ops.
https://lore.kernel.org/patchwork/cover/1271660/
2.30.0.478.g8a0d178c01-goog
Add a new function, get_swiotlb_start(), and remove external access to
io_tlb_start, so we can entirely hide struct swiotlb inside of swiotlb.c
in the following patches.
Signed-off-by: Claire Chang <redacted>
---
arch/powerpc/platforms/pseries/svm.c | 4 ++--
drivers/xen/swiotlb-xen.c | 4 ++--
include/linux/swiotlb.h | 1 +
kernel/dma/swiotlb.c | 5 +++++
4 files changed, 10 insertions(+), 4 deletions(-)
Move is_swiotlb_buffer() to swiotlb.c and make io_tlb_{start,end}
static, so we can entirely hide struct swiotlb inside of swiotlb.c in
the following patches.
Signed-off-by: Claire Chang <redacted>
---
include/linux/swiotlb.h | 7 +------
kernel/dma/swiotlb.c | 7 ++++++-
2 files changed, 7 insertions(+), 7 deletions(-)
Added a new struct, swiotlb, as the IO TLB memory pool descriptor and
moved relevant global variables into that struct.
This will be useful later to allow for restricted DMA pool.
Signed-off-by: Claire Chang <redacted>
---
kernel/dma/swiotlb.c | 327 +++++++++++++++++++++++--------------------
1 file changed, 172 insertions(+), 155 deletions(-)
@@ -200,57 +202,61 @@ void swiotlb_print_info(void)*/void__initswiotlb_update_mem_attributes(void){+structswiotlb*swiotlb=&default_swiotlb;void*vaddr;unsignedlongbytes;if(no_iotlb_memory||late_alloc)return;-vaddr=phys_to_virt(io_tlb_start);-bytes=PAGE_ALIGN(io_tlb_nslabs<<IO_TLB_SHIFT);+vaddr=phys_to_virt(swiotlb->start);+bytes=PAGE_ALIGN(swiotlb->nslabs<<IO_TLB_SHIFT);set_memory_decrypted((unsignedlong)vaddr,bytes>>PAGE_SHIFT);memset(vaddr,0,bytes);}int__initswiotlb_init_with_tbl(char*tlb,unsignedlongnslabs,intverbose){+structswiotlb*swiotlb=&default_swiotlb;unsignedlongi,bytes;size_talloc_size;bytes=nslabs<<IO_TLB_SHIFT;-io_tlb_nslabs=nslabs;-io_tlb_start=__pa(tlb);-io_tlb_end=io_tlb_start+bytes;+swiotlb->nslabs=nslabs;+swiotlb->start=__pa(tlb);+swiotlb->end=swiotlb->start+bytes;/**Allocateandinitializethefreelistarray.Thisarrayisused*tofindcontiguousfreememoryregionsofsizeuptoIO_TLB_SEGSIZE-*betweenio_tlb_startandio_tlb_end.+*betweenswiotlb->startandswiotlb->end.*/-alloc_size=PAGE_ALIGN(io_tlb_nslabs*sizeof(int));-io_tlb_list=memblock_alloc(alloc_size,PAGE_SIZE);-if(!io_tlb_list)+alloc_size=PAGE_ALIGN(swiotlb->nslabs*sizeof(int));+swiotlb->list=memblock_alloc(alloc_size,PAGE_SIZE);+if(!swiotlb->list)panic("%s: Failed to allocate %zu bytes align=0x%lx\n",__func__,alloc_size,PAGE_SIZE);-alloc_size=PAGE_ALIGN(io_tlb_nslabs*sizeof(phys_addr_t));-io_tlb_orig_addr=memblock_alloc(alloc_size,PAGE_SIZE);-if(!io_tlb_orig_addr)+alloc_size=PAGE_ALIGN(swiotlb->nslabs*sizeof(phys_addr_t));+swiotlb->orig_addr=memblock_alloc(alloc_size,PAGE_SIZE);+if(!swiotlb->orig_addr)panic("%s: Failed to allocate %zu bytes align=0x%lx\n",__func__,alloc_size,PAGE_SIZE);-for(i=0;i<io_tlb_nslabs;i++){-io_tlb_list[i]=IO_TLB_SEGSIZE-OFFSET(i,IO_TLB_SEGSIZE);-io_tlb_orig_addr[i]=INVALID_PHYS_ADDR;+for(i=0;i<swiotlb->nslabs;i++){+swiotlb->list[i]=IO_TLB_SEGSIZE-OFFSET(i,IO_TLB_SEGSIZE);+swiotlb->orig_addr[i]=INVALID_PHYS_ADDR;}-io_tlb_index=0;+swiotlb->index=0;no_iotlb_memory=false;if(verbose)swiotlb_print_info();-swiotlb_set_max_segment(io_tlb_nslabs<<IO_TLB_SHIFT);+swiotlb_set_max_segment(swiotlb->nslabs<<IO_TLB_SHIFT);+spin_lock_init(&swiotlb->lock);+return0;}
@@ -261,26 +267,27 @@ int __init swiotlb_init_with_tbl(char *tlb, unsigned long nslabs, int verbose)void__initswiotlb_init(intverbose){+structswiotlb*swiotlb=&default_swiotlb;size_tdefault_size=IO_TLB_DEFAULT_SIZE;unsignedchar*vstart;unsignedlongbytes;-if(!io_tlb_nslabs){-io_tlb_nslabs=(default_size>>IO_TLB_SHIFT);-io_tlb_nslabs=ALIGN(io_tlb_nslabs,IO_TLB_SEGSIZE);+if(!swiotlb->nslabs){+swiotlb->nslabs=(default_size>>IO_TLB_SHIFT);+swiotlb->nslabs=ALIGN(swiotlb->nslabs,IO_TLB_SEGSIZE);}-bytes=io_tlb_nslabs<<IO_TLB_SHIFT;+bytes=swiotlb->nslabs<<IO_TLB_SHIFT;/* Get IO TLB memory from the low pages */vstart=memblock_alloc_low(PAGE_ALIGN(bytes),PAGE_SIZE);-if(vstart&&!swiotlb_init_with_tbl(vstart,io_tlb_nslabs,verbose))+if(vstart&&!swiotlb_init_with_tbl(vstart,swiotlb->nslabs,verbose))return;-if(io_tlb_start){-memblock_free_early(io_tlb_start,-PAGE_ALIGN(io_tlb_nslabs<<IO_TLB_SHIFT));-io_tlb_start=0;+if(swiotlb->start){+memblock_free_early(swiotlb->start,+PAGE_ALIGN(swiotlb->nslabs<<IO_TLB_SHIFT));+swiotlb->start=0;}pr_warn("Cannot allocate buffer");no_iotlb_memory=true;
@@ -83,6 +83,20 @@ config SWIOTLBboolselectNEED_DMA_MAP_STATE+configDMA_RESTRICTED_POOL+bool"DMA Restricted Pool"+depends onOF&&OF_RESERVED_MEM+selectSWIOTLB+help+ThisenablessupportforrestrictedDMApoolswhichprovidealevelof+DMAmemoryprotectiononsystemswithlimitedhardwareprotection+capabilities,suchasthoselackinganIOMMU.++Formoreinformationsee+<Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt>+and<kernel/dma/swiotlb.c>.+Ifunsure,say"n".+## Should be selected if we can mmap non-coherent mappings to userspace.# The only thing that is really required is a way to set an uncached bit
@@ -780,3 +788,87 @@ static int __init swiotlb_create_default_debugfs(void)late_initcall(swiotlb_create_default_debugfs);#endif++#ifdef CONFIG_DMA_RESTRICTED_POOL+staticintrmem_swiotlb_device_init(structreserved_mem*rmem,+structdevice*dev)+{+structswiotlb*swiotlb=rmem->priv;+intret;++if(dev->dev_swiotlb)+return-EBUSY;++/* Since multiple devices can share the same pool, the private data,+*swiotlbstruct,willbeinitializedbythefirstdeviceattached+*toit.+*/+if(!swiotlb){+swiotlb=kzalloc(sizeof(*swiotlb),GFP_KERNEL);+if(!swiotlb)+return-ENOMEM;+#ifdef CONFIG_ARM+unsignedlongpfn=PHYS_PFN(reme->base);++if(!PageHighMem(pfn_to_page(pfn))){+ret=-EINVAL;+gotocleanup;+}+#endif /* CONFIG_ARM */++ret=swiotlb_init_tlb_pool(swiotlb,rmem->base,rmem->size);+if(ret)+gotocleanup;++rmem->priv=swiotlb;+}++#ifdef CONFIG_DEBUG_FS+swiotlb_create_debugfs(swiotlb,rmem->name,default_swiotlb.debugfs);+#endif /* CONFIG_DEBUG_FS */++dev->dev_swiotlb=swiotlb;++return0;++cleanup:+kfree(swiotlb);++returnret;+}++staticvoidrmem_swiotlb_device_release(structreserved_mem*rmem,+structdevice*dev)+{+if(!dev)+return;++#ifdef CONFIG_DEBUG_FS+debugfs_remove_recursive(dev->dev_swiotlb->debugfs);+#endif /* CONFIG_DEBUG_FS */+dev->dev_swiotlb=NULL;+}++staticconststructreserved_mem_opsrmem_swiotlb_ops={+.device_init=rmem_swiotlb_device_init,+.device_release=rmem_swiotlb_device_release,+};++staticint__initrmem_swiotlb_setup(structreserved_mem*rmem)+{+unsignedlongnode=rmem->fdt_node;++if(of_get_flat_dt_prop(node,"reusable",NULL)||+of_get_flat_dt_prop(node,"linux,cma-default",NULL)||+of_get_flat_dt_prop(node,"linux,dma-default",NULL)||+of_get_flat_dt_prop(node,"no-map",NULL))+return-EINVAL;++rmem->ops=&rmem_swiotlb_ops;+pr_info("Reserved memory: created device swiotlb memory pool at %pa, size %ld MiB\n",+&rmem->base,(unsignedlong)rmem->size/SZ_1M);+return0;+}++RESERVEDMEM_OF_DECLARE(dma,"restricted-dma-pool",rmem_swiotlb_setup);+#endif /* CONFIG_DMA_RESTRICTED_POOL */
@@ -495,7 +495,7 @@ int dma_direct_supported(struct device *dev, u64 mask)size_tdma_direct_max_mapping_size(structdevice*dev){/* If SWIOTLB is active, use its maximum mapping size */-if(is_swiotlb_active()&&+if(is_swiotlb_active(dev)&&(dma_addressing_limited(dev)||swiotlb_force==SWIOTLB_FORCE))returnswiotlb_max_mapping_size(dev);returnSIZE_MAX;
@@ -531,15 +529,6 @@ phys_addr_t swiotlb_tbl_map_single(struct device *hwdev, phys_addr_t orig_addr,#endifpanic("Can not allocate SWIOTLB buffer earlier and can't now provide you with the DMA bounce buffer");-if(mem_encrypt_active())-pr_warn_once("Memory encryption is active and system is using DMA bounce buffers\n");--if(mapping_size>alloc_size){-dev_warn_once(hwdev,"Invalid sizes (mapping: %zd bytes, alloc: %zd bytes)",-mapping_size,alloc_size);-return(phys_addr_t)DMA_MAPPING_ERROR;-}-mask=dma_get_seg_boundary(hwdev);tbl_dma_addr&=mask;
@@ -624,45 +612,20 @@ phys_addr_t swiotlb_tbl_map_single(struct device *hwdev, phys_addr_t orig_addr,if(!(attrs&DMA_ATTR_NO_WARN)&&printk_ratelimit())dev_warn(hwdev,"swiotlb buffer is full (sz: %zd bytes), total %lu (slots), used %lu (slots)\n",alloc_size,swiotlb->nslabs,tmp_io_tlb_used);-return(phys_addr_t)DMA_MAPPING_ERROR;+return-ENOMEM;+found:swiotlb->used+=nslots;spin_unlock_irqrestore(&swiotlb->lock,flags);-/*-*SaveawaythemappingfromtheoriginaladdresstotheDMAaddress.-*Thisisneededwhenwesyncthememory.Thenwesyncthebufferif-*needed.-*/-for(i=0;i<nslots;i++)-swiotlb->orig_addr[index+i]=orig_addr+(i<<IO_TLB_SHIFT);-if(!(attrs&DMA_ATTR_SKIP_CPU_SYNC)&&-(dir==DMA_TO_DEVICE||dir==DMA_BIDIRECTIONAL))-swiotlb_bounce(orig_addr,tlb_addr,mapping_size,DMA_TO_DEVICE);--returntlb_addr;+returnindex;}-/*-*tlb_addristhephysicaladdressofthebouncebuffertounmap.-*/-voidswiotlb_tbl_unmap_single(structdevice*hwdev,phys_addr_ttlb_addr,-size_tmapping_size,size_talloc_size,-enumdma_data_directiondir,unsignedlongattrs)+staticvoidswiotlb_tbl_release_region(structdevice*hwdev,intindex,size_tsize){structswiotlb*swiotlb=get_swiotlb(hwdev);unsignedlongflags;-inti,count,nslots=ALIGN(alloc_size,1<<IO_TLB_SHIFT)>>IO_TLB_SHIFT;-intindex=(tlb_addr-swiotlb->start)>>IO_TLB_SHIFT;-phys_addr_torig_addr=swiotlb->orig_addr[index];--/*-*First,syncthememorybeforeunmappingtheentry-*/-if(orig_addr!=INVALID_PHYS_ADDR&&-!(attrs&DMA_ATTR_SKIP_CPU_SYNC)&&-((dir==DMA_FROM_DEVICE)||(dir==DMA_BIDIRECTIONAL)))-swiotlb_bounce(orig_addr,tlb_addr,mapping_size,DMA_FROM_DEVICE);+inti,count,nslots=ALIGN(size,1<<IO_TLB_SHIFT)>>IO_TLB_SHIFT;/**Returnthebuffertothefreelistbysettingthecorresponding
@@ -694,6 +657,69 @@ void swiotlb_tbl_unmap_single(struct device *hwdev, phys_addr_t tlb_addr,spin_unlock_irqrestore(&swiotlb->lock,flags);}+phys_addr_tswiotlb_tbl_map_single(structdevice*hwdev,phys_addr_torig_addr,+size_tmapping_size,size_talloc_size,+enumdma_data_directiondir,+unsignedlongattrs)+{+structswiotlb*swiotlb=get_swiotlb(hwdev);+dma_addr_ttbl_dma_addr=phys_to_dma_unencrypted(hwdev,swiotlb->start);+phys_addr_ttlb_addr;+unsignedintnslots,index;+inti;++if(mem_encrypt_active())+pr_warn_once("Memory encryption is active and system is using DMA bounce buffers\n");++if(mapping_size>alloc_size){+dev_warn_once(hwdev,"Invalid sizes (mapping: %zd bytes, alloc: %zd bytes)",+mapping_size,alloc_size);+return(phys_addr_t)DMA_MAPPING_ERROR;+}++index=swiotlb_tbl_find_free_region(hwdev,tbl_dma_addr,alloc_size,attrs);+if(index<0)+return(phys_addr_t)DMA_MAPPING_ERROR;++tlb_addr=swiotlb->start+(index<<IO_TLB_SHIFT);++/*+*SaveawaythemappingfromtheoriginaladdresstotheDMAaddress.+*Thisisneededwhenwesyncthememory.Thenwesyncthebufferif+*needed.+*/+nslots=ALIGN(alloc_size,1<<IO_TLB_SHIFT)>>IO_TLB_SHIFT;+for(i=0;i<nslots;i++)+swiotlb->orig_addr[index+i]=orig_addr+(i<<IO_TLB_SHIFT);+if(!(attrs&DMA_ATTR_SKIP_CPU_SYNC)&&+(dir==DMA_TO_DEVICE||dir==DMA_BIDIRECTIONAL))+swiotlb_bounce(orig_addr,tlb_addr,mapping_size,DMA_TO_DEVICE);++returntlb_addr;+}++/*+*tlb_addristhephysicaladdressofthebouncebuffertounmap.+*/+voidswiotlb_tbl_unmap_single(structdevice*hwdev,phys_addr_ttlb_addr,+size_tmapping_size,size_talloc_size,+enumdma_data_directiondir,unsignedlongattrs)+{+structswiotlb*swiotlb=get_swiotlb(hwdev);+intindex=(tlb_addr-swiotlb->start)>>IO_TLB_SHIFT;+phys_addr_torig_addr=swiotlb->orig_addr[index];++/*+*First,syncthememorybeforeunmappingtheentry+*/+if(orig_addr!=INVALID_PHYS_ADDR&&+!(attrs&DMA_ATTR_SKIP_CPU_SYNC)&&+((dir==DMA_FROM_DEVICE)||(dir==DMA_BIDIRECTIONAL)))+swiotlb_bounce(orig_addr,tlb_addr,mapping_size,DMA_FROM_DEVICE);++swiotlb_tbl_release_region(hwdev,index,alloc_size);+}+voidswiotlb_tbl_sync_single(structdevice*hwdev,phys_addr_ttlb_addr,size_tsize,enumdma_data_directiondir,enumdma_sync_targettarget)
Add a new wrapper __dma_direct_free_pages() that will be useful later
for dev_swiotlb_free().
Signed-off-by: Claire Chang <redacted>
---
kernel/dma/direct.c | 13 +++++++++----
1 file changed, 9 insertions(+), 4 deletions(-)
Introduce the new compatible string, restricted-dma-pool, for restricted
DMA. One can specify the address and length of the restricted DMA memory
region by restricted-dma-pool in the reserved-memory node.
Signed-off-by: Claire Chang <redacted>
---
.../reserved-memory/reserved-memory.txt | 24 +++++++++++++++++++
1 file changed, 24 insertions(+)
@@ -51,6 +51,20 @@ compatible (optional) - standard definition used as a shared pool of DMA buffers for a set of devices. It can be used by an operating system to instantiate the necessary pool management subsystem if necessary.+ - restricted-dma-pool: This indicates a region of memory meant to be+ used as a pool of restricted DMA buffers for a set of devices. The+ memory region would be the only region accessible to those devices.+ When using this, the no-map and reusable properties must not be set,+ so the operating system can create a virtual mapping that will be used+ for synchronization. The main purpose for restricted DMA is to+ mitigate the lack of DMA access control on systems without an IOMMU,+ which could result in the DMA accessing the system memory at+ unexpected times and/or unexpected addresses, possibly leading to data+ leakage or corruption. The feature on its own provides a basic level+ of protection against the DMA overwriting buffer contents at+ unexpected times. However, to protect against general data leakage and+ system memory corruption, the system needs to provide way to lock down+ the memory access, e.g., MPU. - vendor specific string in the form <vendor>,[<device>-]<usage> no-map (optional) - empty property - Indicates the operating system must not create a virtual mapping
From: Will Deacon <will@kernel.org> Date: 2021-03-10 16:08:53
Hi Claire,
On Tue, Feb 09, 2021 at 02:21:30PM +0800, Claire Chang wrote:
quoted hunk
Introduce the new compatible string, restricted-dma-pool, for restricted
DMA. One can specify the address and length of the restricted DMA memory
region by restricted-dma-pool in the reserved-memory node.
Signed-off-by: Claire Chang <redacted>
---
.../reserved-memory/reserved-memory.txt | 24 +++++++++++++++++++
1 file changed, 24 insertions(+)
@@ -51,6 +51,20 @@ compatible (optional) - standard definition used as a shared pool of DMA buffers for a set of devices. It can be used by an operating system to instantiate the necessary pool management subsystem if necessary.+ - restricted-dma-pool: This indicates a region of memory meant to be+ used as a pool of restricted DMA buffers for a set of devices. The+ memory region would be the only region accessible to those devices.+ When using this, the no-map and reusable properties must not be set,+ so the operating system can create a virtual mapping that will be used+ for synchronization. The main purpose for restricted DMA is to+ mitigate the lack of DMA access control on systems without an IOMMU,+ which could result in the DMA accessing the system memory at+ unexpected times and/or unexpected addresses, possibly leading to data+ leakage or corruption. The feature on its own provides a basic level+ of protection against the DMA overwriting buffer contents at+ unexpected times. However, to protect against general data leakage and+ system memory corruption, the system needs to provide way to lock down+ the memory access, e.g., MPU.
As far as I can tell, these pools work with both static allocations (which
seem to match your use-case where firmware has preconfigured the DMA ranges)
but also with dynamic allocations where a 'size' property is present instead
of the 'reg' property and the kernel is responsible for allocating the
reservation during boot. Am I right and, if so, is that deliberate?
I ask because I think that would potentially be useful to us for the
Protected KVM work, where we need to bounce virtio memory accesses via
guest-determined windows because the guest memory is generally inaccessible
to the host. We've been hacking this using a combination of "swiotlb=force"
and set_memory_{decrypted,encrypted}() but it would be much better to
leverage the stuff you have here.
Also:
I find this example a bit weird, as I didn't think we usually had DT nodes
for PCI devices; rather they are discovered as a result of probing config
space. Is the idea that you have one reserved memory region attached to the
RC and all the PCI devices below that share the region, or is there a need
for a mapping mechanism?
Will
From: Rob Herring <robh+dt@kernel.org> Date: 2021-03-10 21:41:45
On Wed, Mar 10, 2021 at 9:08 AM Will Deacon [off-list ref] wrote:
Hi Claire,
On Tue, Feb 09, 2021 at 02:21:30PM +0800, Claire Chang wrote:
quoted
Introduce the new compatible string, restricted-dma-pool, for restricted
DMA. One can specify the address and length of the restricted DMA memory
region by restricted-dma-pool in the reserved-memory node.
Signed-off-by: Claire Chang <redacted>
---
.../reserved-memory/reserved-memory.txt | 24 +++++++++++++++++++
1 file changed, 24 insertions(+)
@@ -51,6 +51,20 @@ compatible (optional) - standard definition used as a shared pool of DMA buffers for a set of devices. It can be used by an operating system to instantiate the necessary pool management subsystem if necessary.+ - restricted-dma-pool: This indicates a region of memory meant to be+ used as a pool of restricted DMA buffers for a set of devices. The+ memory region would be the only region accessible to those devices.+ When using this, the no-map and reusable properties must not be set,+ so the operating system can create a virtual mapping that will be used+ for synchronization. The main purpose for restricted DMA is to+ mitigate the lack of DMA access control on systems without an IOMMU,+ which could result in the DMA accessing the system memory at+ unexpected times and/or unexpected addresses, possibly leading to data+ leakage or corruption. The feature on its own provides a basic level+ of protection against the DMA overwriting buffer contents at+ unexpected times. However, to protect against general data leakage and+ system memory corruption, the system needs to provide way to lock down+ the memory access, e.g., MPU.
As far as I can tell, these pools work with both static allocations (which
seem to match your use-case where firmware has preconfigured the DMA ranges)
but also with dynamic allocations where a 'size' property is present instead
of the 'reg' property and the kernel is responsible for allocating the
reservation during boot. Am I right and, if so, is that deliberate?
I believe so. I'm not keen on having size only reservations in DT.
Yes, we allowed that already, but that's back from the days of needing
large CMA carveouts to be reserved early in boot. I've read that the
kernel is much better now at contiguous allocations, so do we really
need this in DT anymore?
I ask because I think that would potentially be useful to us for the
Protected KVM work, where we need to bounce virtio memory accesses via
guest-determined windows because the guest memory is generally inaccessible
to the host. We've been hacking this using a combination of "swiotlb=force"
and set_memory_{decrypted,encrypted}() but it would be much better to
leverage the stuff you have here.
Also:
I find this example a bit weird, as I didn't think we usually had DT nodes
for PCI devices; rather they are discovered as a result of probing config
space. Is the idea that you have one reserved memory region attached to the
RC and all the PCI devices below that share the region, or is there a need
for a mapping mechanism?
We can have DT nodes for PCI. AIUI, IBM power systems always do. For
FDT, it's only if there are extra non-discoverable resources. It's
particularly fun when it's resources which need to be enabled for the
PCI device to be discovered. That seems to be a growing problem as PCI
becomes more common on embedded systems.
Rob
On Wed, Mar 10, 2021 at 9:08 AM Will Deacon [off-list ref] wrote:
quoted
Hi Claire,
On Tue, Feb 09, 2021 at 02:21:30PM +0800, Claire Chang wrote:
quoted
Introduce the new compatible string, restricted-dma-pool, for restricted
DMA. One can specify the address and length of the restricted DMA memory
region by restricted-dma-pool in the reserved-memory node.
Signed-off-by: Claire Chang <redacted>
---
.../reserved-memory/reserved-memory.txt | 24 +++++++++++++++++++
1 file changed, 24 insertions(+)
@@ -51,6 +51,20 @@ compatible (optional) - standard definition used as a shared pool of DMA buffers for a set of devices. It can be used by an operating system to instantiate the necessary pool management subsystem if necessary.+ - restricted-dma-pool: This indicates a region of memory meant to be+ used as a pool of restricted DMA buffers for a set of devices. The+ memory region would be the only region accessible to those devices.+ When using this, the no-map and reusable properties must not be set,+ so the operating system can create a virtual mapping that will be used+ for synchronization. The main purpose for restricted DMA is to+ mitigate the lack of DMA access control on systems without an IOMMU,+ which could result in the DMA accessing the system memory at+ unexpected times and/or unexpected addresses, possibly leading to data+ leakage or corruption. The feature on its own provides a basic level+ of protection against the DMA overwriting buffer contents at+ unexpected times. However, to protect against general data leakage and+ system memory corruption, the system needs to provide way to lock down+ the memory access, e.g., MPU.
As far as I can tell, these pools work with both static allocations (which
seem to match your use-case where firmware has preconfigured the DMA ranges)
but also with dynamic allocations where a 'size' property is present instead
of the 'reg' property and the kernel is responsible for allocating the
reservation during boot. Am I right and, if so, is that deliberate?
I believe so. I'm not keen on having size only reservations in DT.
Yes, we allowed that already, but that's back from the days of needing
large CMA carveouts to be reserved early in boot. I've read that the
kernel is much better now at contiguous allocations, so do we really
need this in DT anymore?
I would say yes, there can be a number of times where you want to semi
statically partition your physical memory and their reserved regions. Be
it to pack everything together under the same protection rules or
because you need to allocate memory from a particular address range in
say a non-uniform memory controller architecture where address windows
have different scheduling algorithms.
--
Florian
Regardless of swiotlb setting, the restricted DMA pool is preferred if
available.
The restricted DMA pools provide a basic level of protection against the
DMA overwriting buffer contents at unexpected times. However, to protect
against general data leakage and system memory corruption, the system
needs to provide a way to lock down the memory access, e.g., MPU.
Signed-off-by: Claire Chang <redacted>
---
include/linux/swiotlb.h | 13 +++++++++++++
kernel/dma/direct.h | 2 +-
kernel/dma/swiotlb.c | 20 +++++++++++++++++---
3 files changed, 31 insertions(+), 4 deletions(-)
@@ -519,7 +524,11 @@ phys_addr_t swiotlb_tbl_map_single(struct device *hwdev, phys_addr_t orig_addr,unsignedlongmax_slots;unsignedlongtmp_io_tlb_used;+#ifdef CONFIG_DMA_RESTRICTED_POOL+if(no_iotlb_memory&&!hwdev->dev_swiotlb)+#elseif(no_iotlb_memory)+#endifpanic("Can not allocate SWIOTLB buffer earlier and can't now provide you with the DMA bounce buffer");if(mem_encrypt_active())
@@ -171,7 +182,9 @@ void *dma_direct_alloc(struct device *dev, size_t size,if(IS_ENABLED(CONFIG_DMA_COHERENT_POOL)&&!gfpflags_allow_blocking(gfp)&&(force_dma_unencrypted(dev)||-(IS_ENABLED(CONFIG_DMA_DIRECT_REMAP)&&!dev_is_dma_coherent(dev))))+(IS_ENABLED(CONFIG_DMA_DIRECT_REMAP)&&+!dev_is_dma_coherent(dev)))&&+!is_dev_swiotlb_force(dev))returndma_direct_alloc_from_pool(dev,size,dma_handle,gfp);/* we always manually zero the memory once we are done */
@@ -252,15 +265,15 @@ void dma_direct_free(struct device *dev, size_t size,unsignedintpage_order=get_order(size);if((attrs&DMA_ATTR_NO_KERNEL_MAPPING)&&-!force_dma_unencrypted(dev)){+!force_dma_unencrypted(dev)&&!is_dev_swiotlb_force(dev)){/* cpu_addr is a struct page cookie, not a kernel address */dma_free_contiguous(dev,cpu_addr,size);return;}if(!IS_ENABLED(CONFIG_ARCH_HAS_DMA_SET_UNCACHED)&&-!IS_ENABLED(CONFIG_DMA_DIRECT_REMAP)&&-!dev_is_dma_coherent(dev)){+!IS_ENABLED(CONFIG_DMA_DIRECT_REMAP)&&!dev_is_dma_coherent(dev)&&+!is_dev_swiotlb_force(dev)){arch_dma_free(dev,size,cpu_addr,dma_addr,attrs);return;}
@@ -836,6 +836,40 @@ late_initcall(swiotlb_create_default_debugfs);#endif#ifdef CONFIG_DMA_RESTRICTED_POOL+structpage*dev_swiotlb_alloc(structdevice*dev,size_tsize,gfp_tgfp)+{+structswiotlb*swiotlb;+phys_addr_ttlb_addr;+unsignedintindex;++/* dev_swiotlb_alloc can be used only in the context which permits sleeping. */+if(!dev->dev_swiotlb||!gfpflags_allow_blocking(gfp))+returnNULL;++swiotlb=dev->dev_swiotlb;+index=swiotlb_tbl_find_free_region(dev,swiotlb->start,size,0);+if(index<0)+returnNULL;++tlb_addr=swiotlb->start+(index<<IO_TLB_SHIFT);++returnpfn_to_page(PFN_DOWN(tlb_addr));+}++booldev_swiotlb_free(structdevice*dev,structpage*page,size_tsize)+{+unsignedintindex;+phys_addr_ttlb_addr=page_to_phys(page);++if(!is_swiotlb_buffer(dev,tlb_addr))+returnfalse;++index=(tlb_addr-dev->dev_swiotlb->start)>>IO_TLB_SHIFT;+swiotlb_tbl_release_region(dev,index,size);++returntrue;+}+boolis_swiotlb_force(structdevice*dev){returnunlikely(swiotlb_force==SWIOTLB_FORCE)||dev->dev_swiotlb;
@@ -836,6 +836,40 @@ late_initcall(swiotlb_create_default_debugfs);#endif#ifdef CONFIG_DMA_RESTRICTED_POOL+structpage*dev_swiotlb_alloc(structdevice*dev,size_tsize,gfp_tgfp)+{+structswiotlb*swiotlb;+phys_addr_ttlb_addr;+unsignedintindex;++/* dev_swiotlb_alloc can be used only in the context which permits sleeping. */+if(!dev->dev_swiotlb||!gfpflags_allow_blocking(gfp))
Just noticed that !gfpflags_allow_blocking(gfp) shouldn't be here.
Hi Christoph,
Do you think I should fix this and rebase on the latest linux-next
now? I wonder if there are more factor and clean up coming and I
should wait after that.
Thanks,
Claire
From: Christoph Hellwig <hch@lst.de> Date: 2021-02-26 05:18:42
On Fri, Feb 26, 2021 at 12:17:50PM +0800, Claire Chang wrote:
Do you think I should fix this and rebase on the latest linux-next
now? I wonder if there are more factor and clean up coming and I
should wait after that.
Here is my preferred plan:
1) wait for my series to support the min alignment in swiotlb to
land in Linus tree
2) I'll resend my series with the further swiotlb cleanup and
refactoring, which includes a slightly rebased version of your
patch to add the io_tlb_mem structure
3) resend your series on top of that as a baseline
This is my current WIP tree for 2:
http://git.infradead.org/users/hch/misc.git/shortlog/refs/heads/swiotlb-struct
On Fri, Feb 26, 2021 at 1:17 PM Christoph Hellwig [off-list ref] wrote:
On Fri, Feb 26, 2021 at 12:17:50PM +0800, Claire Chang wrote:
quoted
Do you think I should fix this and rebase on the latest linux-next
now? I wonder if there are more factor and clean up coming and I
should wait after that.
Here is my preferred plan:
1) wait for my series to support the min alignment in swiotlb to
land in Linus tree
2) I'll resend my series with the further swiotlb cleanup and
refactoring, which includes a slightly rebased version of your
patch to add the io_tlb_mem structure
3) resend your series on top of that as a baseline
This is my current WIP tree for 2:
http://git.infradead.org/users/hch/misc.git/shortlog/refs/heads/swiotlb-struct
If a device is not behind an IOMMU, we look up the device node and set
up the restricted DMA when the restricted-dma-pool is presented.
Signed-off-by: Claire Chang <redacted>
---
drivers/of/address.c | 25 +++++++++++++++++++++++++
drivers/of/device.c | 3 +++
drivers/of/of_private.h | 5 +++++
3 files changed, 33 insertions(+)
@@ -1094,3 +1095,27 @@ bool of_dma_is_coherent(struct device_node *np)returnfalse;}EXPORT_SYMBOL_GPL(of_dma_is_coherent);++intof_dma_set_restricted_buffer(structdevice*dev)+{+structdevice_node*node;+intcount,i;++if(!dev->of_node)+return0;++count=of_property_count_elems_of_size(dev->of_node,"memory-region",+sizeof(phandle));+for(i=0;i<count;i++){+node=of_parse_phandle(dev->of_node,"memory-region",i);+/* There might be multiple memory regions, but only one+*restriced-dma-poolregionisallowed.+*/+if(of_device_is_compatible(node,"restricted-dma-pool")&&+of_device_is_available(node))+returnof_reserved_mem_device_init_by_idx(+dev,dev->of_node,i);+}++return0;+}
From: David Woodhouse <dwmw2@infradead.org> Date: 2025-03-21 15:38:43
On Tue, 2021-02-09 at 14:21 +0800, Claire Chang wrote:
This series implements mitigations for lack of DMA access control on
systems without an IOMMU, which could result in the DMA accessing the
system memory at unexpected times and/or unexpected addresses, possibly
leading to data leakage or corruption.
Replying to an ancient (2021) thread which has already been merged...
I'd like to be able to use this facility for virtio devices.
Virtio already has a complicated relationship with the DMA API, because
there were a bunch of early VMM bugs where the virtio devices where
magically exempted from IOMMU protection, but the VMM lied to the guest
and claimed they weren't.
With the advent of confidential computing, and the VMM (or whatever's
emulating the virtio device) not being *allowed* to arbitrarily access
all of the guest's memory, the DMA API becomes necessary again.
Either a virtual IOMMU needs to determine which guest memory the VMM
may access, or the DMA API is wrappers around operations which
share/unshare (or unencrypt/encrypt) the memory in question.
All of which is complicated and slow, if we're looking at a minimal
privileged hypervisor stub like pKVM which enforces the lack of guest
memory access from VMM.
I'm thinking of defining a new type of virtio-pci device which cannot
do DMA to arbitrary system memory. Instead it has an additional memory
BAR which is used as a SWIOTLB for bounce buffering.
The driver for it would look much like the existing virtio-pci device
except that it would register the restricted-dma region first (and thus
the swiotlb dma_ops), and then just go through the rest of the setup
like any other virtio device.
That seems like it ought to be fairly simple, and seems like a
reasonable way to allow an untrusted VMM to provide virtio devices with
restricted DMA access.
While I start actually doing the typing... does anyone want to start
yelling at me now? Christoph? mst? :)
From: "Michael S. Tsirkin" <mst@redhat.com> Date: 2025-03-21 18:32:45
On Fri, Mar 21, 2025 at 03:38:10PM +0000, David Woodhouse wrote:
On Tue, 2021-02-09 at 14:21 +0800, Claire Chang wrote:
quoted
This series implements mitigations for lack of DMA access control on
systems without an IOMMU, which could result in the DMA accessing the
system memory at unexpected times and/or unexpected addresses, possibly
leading to data leakage or corruption.
Replying to an ancient (2021) thread which has already been merged...
I'd like to be able to use this facility for virtio devices.
Virtio already has a complicated relationship with the DMA API, because
there were a bunch of early VMM bugs where the virtio devices where
magically exempted from IOMMU protection, but the VMM lied to the guest
and claimed they weren't.
With the advent of confidential computing, and the VMM (or whatever's
emulating the virtio device) not being *allowed* to arbitrarily access
all of the guest's memory, the DMA API becomes necessary again.
Either a virtual IOMMU needs to determine which guest memory the VMM
may access, or the DMA API is wrappers around operations which
share/unshare (or unencrypt/encrypt) the memory in question.
All of which is complicated and slow, if we're looking at a minimal
privileged hypervisor stub like pKVM which enforces the lack of guest
memory access from VMM.
I'm thinking of defining a new type of virtio-pci device which cannot
do DMA to arbitrary system memory. Instead it has an additional memory
BAR which is used as a SWIOTLB for bounce buffering.
The driver for it would look much like the existing virtio-pci device
except that it would register the restricted-dma region first (and thus
the swiotlb dma_ops), and then just go through the rest of the setup
like any other virtio device.
That seems like it ought to be fairly simple, and seems like a
reasonable way to allow an untrusted VMM to provide virtio devices with
restricted DMA access.
While I start actually doing the typing... does anyone want to start
yelling at me now? Christoph? mst? :)
I don't mind as such (though I don't understand completely), but since
this is changing the device anyway, I am a bit confused why you can't
just set the VIRTIO_F_ACCESS_PLATFORM feature bit? This forces DMA API
which will DTRT for you, will it not?
--
MST
From: David Woodhouse <dwmw2@infradead.org> Date: 2025-03-21 18:42:51
On Fri, 2025-03-21 at 14:32 -0400, Michael S. Tsirkin wrote:
On Fri, Mar 21, 2025 at 03:38:10PM +0000, David Woodhouse wrote:
quoted
On Tue, 2021-02-09 at 14:21 +0800, Claire Chang wrote:
quoted
This series implements mitigations for lack of DMA access control on
systems without an IOMMU, which could result in the DMA accessing the
system memory at unexpected times and/or unexpected addresses, possibly
leading to data leakage or corruption.
Replying to an ancient (2021) thread which has already been merged...
I'd like to be able to use this facility for virtio devices.
Virtio already has a complicated relationship with the DMA API, because
there were a bunch of early VMM bugs where the virtio devices where
magically exempted from IOMMU protection, but the VMM lied to the guest
and claimed they weren't.
With the advent of confidential computing, and the VMM (or whatever's
emulating the virtio device) not being *allowed* to arbitrarily access
all of the guest's memory, the DMA API becomes necessary again.
Either a virtual IOMMU needs to determine which guest memory the VMM
may access, or the DMA API is wrappers around operations which
share/unshare (or unencrypt/encrypt) the memory in question.
All of which is complicated and slow, if we're looking at a minimal
privileged hypervisor stub like pKVM which enforces the lack of guest
memory access from VMM.
I'm thinking of defining a new type of virtio-pci device which cannot
do DMA to arbitrary system memory. Instead it has an additional memory
BAR which is used as a SWIOTLB for bounce buffering.
The driver for it would look much like the existing virtio-pci device
except that it would register the restricted-dma region first (and thus
the swiotlb dma_ops), and then just go through the rest of the setup
like any other virtio device.
That seems like it ought to be fairly simple, and seems like a
reasonable way to allow an untrusted VMM to provide virtio devices with
restricted DMA access.
While I start actually doing the typing... does anyone want to start
yelling at me now? Christoph? mst? :)
I don't mind as such (though I don't understand completely), but since
this is changing the device anyway, I am a bit confused why you can't
just set the VIRTIO_F_ACCESS_PLATFORM feature bit? This forces DMA API
which will DTRT for you, will it not?
That would be necessary but not sufficient. The question is *what* does
the DMA API do?
For a real passthrough PCI device, perhaps we'd have a vIOMMU exposed
to the guest so that it can do real protection with two-stage page
tables (IOVA→GPA under control of the guest, GPA→HPA under control of
the hypervisor). For that to work in the pKVM model though, you'd need
pKVM to be talking the guest's stage1 I/O page tables to see if a given
access from the VMM ought to be permitted?
Or for confidential guests there could be DMA ops which are an
'enlightenment'; a hypercall into pKVM to share/unshare pages so that
the VMM can actually access them, or SEV-SNP guests might mark pages
unencrypted to have the same effect with hardware protection.
Doing any of those dynamically to allow the VMM to access buffers in
arbitrary guest memory (when it wouldn't normally have access to
arbitrary guest memory) is complex and doesn't perform very well. And
exposes a full 4KiB page for any byte that needs to be made available.
Thus the idea of having a fixed range of memory to use for a SWIOTLB,
which is fairly much what the restricted DMA setup is all about.
We're just proposing that we build it in to a virtio-pci device model,
which automatically uses the extra memory BAR instead of the
restricted-dma-pool DT node.
It's basically just allowing us to expose through PCI, what I believe
we can already do for virtio in DT.
From: David Woodhouse <dwmw2@infradead.org> Date: 2025-03-28 17:41:18
On Fri, 2025-03-21 at 18:42 +0000, David Woodhouse wrote:
On Fri, 2025-03-21 at 14:32 -0400, Michael S. Tsirkin wrote:
quoted
On Fri, Mar 21, 2025 at 03:38:10PM +0000, David Woodhouse wrote:
quoted
On Tue, 2021-02-09 at 14:21 +0800, Claire Chang wrote:
quoted
This series implements mitigations for lack of DMA access control on
systems without an IOMMU, which could result in the DMA accessing the
system memory at unexpected times and/or unexpected addresses, possibly
leading to data leakage or corruption.
Replying to an ancient (2021) thread which has already been merged...
I'd like to be able to use this facility for virtio devices.
Virtio already has a complicated relationship with the DMA API, because
there were a bunch of early VMM bugs where the virtio devices where
magically exempted from IOMMU protection, but the VMM lied to the guest
and claimed they weren't.
With the advent of confidential computing, and the VMM (or whatever's
emulating the virtio device) not being *allowed* to arbitrarily access
all of the guest's memory, the DMA API becomes necessary again.
Either a virtual IOMMU needs to determine which guest memory the VMM
may access, or the DMA API is wrappers around operations which
share/unshare (or unencrypt/encrypt) the memory in question.
All of which is complicated and slow, if we're looking at a minimal
privileged hypervisor stub like pKVM which enforces the lack of guest
memory access from VMM.
I'm thinking of defining a new type of virtio-pci device which cannot
do DMA to arbitrary system memory. Instead it has an additional memory
BAR which is used as a SWIOTLB for bounce buffering.
The driver for it would look much like the existing virtio-pci device
except that it would register the restricted-dma region first (and thus
the swiotlb dma_ops), and then just go through the rest of the setup
like any other virtio device.
That seems like it ought to be fairly simple, and seems like a
reasonable way to allow an untrusted VMM to provide virtio devices with
restricted DMA access.
While I start actually doing the typing... does anyone want to start
yelling at me now? Christoph? mst? :)
I don't mind as such (though I don't understand completely), but since
this is changing the device anyway, I am a bit confused why you can't
just set the VIRTIO_F_ACCESS_PLATFORM feature bit? This forces DMA API
which will DTRT for you, will it not?
That would be necessary but not sufficient. ...
My first cut at a proposed spec change looks something like this. I'll
post it to the virtio-comment list once I've done some corporate
bureaucracy and when the list stops sending me python tracebacks in
response to my subscribe request.
In the meantime I'll hack up some QEMU and guest Linux driver support
to match.
@@ -773,6 +773,9 @@ \chapter{Reserved Feature Bits}\label{sec:Reserved Feature Bits} Currently these device-independent feature bits are defined:\begin{description}+\item[VIRTIO_F_SWIOTLB (27)] This feature indicates that the device+ provides a memory region which is to be used for bounce buffering,+ rather than permitting direct memory access to system memory.\item[VIRTIO_F_INDIRECT_DESC (28)] Negotiating this feature indicates that the driver can use descriptors with the VIRTQ_DESC_F_INDIRECT flag set, as described in \ref{sec:Basic Facilities of a Virtio
@@ -885,6 +888,10 @@ \chapter{Reserved Feature Bits}\label{sec:Reserved Feature Bits} VIRTIO_F_ACCESS_PLATFORM is not offered, then a driver MUST pass only physical addresses to the device.+A driver SHOULD accept VIRTIO_F_SWIOTLB if it is offered, and it MUST+then pass only addresses within the Software IOTLB bounce buffer to the+device.+ A driver SHOULD accept VIRTIO_F_RING_PACKED if it is offered. A driver SHOULD accept VIRTIO_F_ORDER_PLATFORM if it is offered.
@@ -921,6 +928,10 @@ \chapter{Reserved Feature Bits}\label{sec:Reserved Feature Bits} A device MAY fail to operate further if VIRTIO_F_ACCESS_PLATFORM is not accepted.+A device MUST NOT offer VIRTIO_F_SWIOTLB if its transport does not+provide a Software IOTLB bounce buffer.+A device MAY fail to operate further if VIRTIO_F_SWIOTLB is not accepted.+ If VIRTIO_F_IN_ORDER has been negotiated, a device MUST use buffers in the same order in which they have been available.
@@ -129,6 +129,7 @@ \subsection{Virtio Structure PCI Capabilities}\label{sec:Virtio Transport Option\item ISR Status\item Device-specific configuration (optional)\item PCI configuration access+\item SWIOTLB bounce buffer\end{itemize} Each structure can be mapped by a Base Address register (BAR) belonging to
@@ -188,6 +189,8 @@ \subsection{Virtio Structure PCI Capabilities}\label{sec:Virtio Transport Option #define VIRTIO_PCI_CAP_SHARED_MEMORY_CFG 8 /* Vendor-specific data */ #define VIRTIO_PCI_CAP_VENDOR_CFG 9+/* Software IOTLB bounce buffer */+#define VIRTIO_PCI_CAP_SWIOTLB 10\end{lstlisting} Any other value is reserved for future use.
@@ -744,6 +747,36 @@ \subsubsection{Vendor data capability}\label{sec:Virtio The driver MUST qualify the \field{vendor_id} before interpreting or writing into the Vendor data capability.+\subsubsection{Software IOTLB bounce buffer capability}\label{sec:Virtio+Transport Options / Virtio Over PCI Bus / PCI Device Layout /+Software IOTLB bounce buffer capability}++The optional Software IOTLB bounce buffer capability allows the+device to provide a memory region which can be used by the driver+driver for bounce buffering. This allows a device on the PCI+transport to operate without DMA access to system memory addresses.++The Software IOTLB region is referenced by the+VIRTIO_PCI_CAP_SWIOTLB capability. Bus addresses within the referenced+range are not subject to the requirements of the VIRTIO_F_ORDER_PLATFORM+capability, if negotiated.++\devicenormative{\paragraph}{Software IOTLB bounce buffer capability}{Virtio+Transport Options / Virtio Over PCI Bus / PCI Device Layout /+Software IOTLB bounce buffer capability}++Devices which present the Software IOTLB bounce buffer capability+SHOULD also offer the VIRTIO_F_SWIOTLB feature.++\drivernormative{\paragraph}{Software IOTLB bounce buffer capability}{Virtio+Transport Options / Virtio Over PCI Bus / PCI Device Layout /+Software IOTLB bounce buffer capability}++The driver SHOULD use the offered buffer in preference to passing system+memory addresses to the device. If the driver accepts the VIRTIO_F_SWIOTLB+feature, then the driver MUST use the offered buffer and never pass system+memory addresses to the device.+\subsubsection{PCI configuration access capability}\label{sec:Virtio Transport Options / Virtio Over PCI Bus / PCI Device Layout / PCI configuration access capability} The VIRTIO_PCI_CAP_PCI_CFG capability
From: "Michael S. Tsirkin" <mst@redhat.com> Date: 2025-03-30 13:42:19
On Fri, Mar 28, 2025 at 05:40:41PM +0000, David Woodhouse wrote:
On Fri, 2025-03-21 at 18:42 +0000, David Woodhouse wrote:
quoted
On Fri, 2025-03-21 at 14:32 -0400, Michael S. Tsirkin wrote:
quoted
On Fri, Mar 21, 2025 at 03:38:10PM +0000, David Woodhouse wrote:
quoted
On Tue, 2021-02-09 at 14:21 +0800, Claire Chang wrote:
quoted
This series implements mitigations for lack of DMA access control on
systems without an IOMMU, which could result in the DMA accessing the
system memory at unexpected times and/or unexpected addresses, possibly
leading to data leakage or corruption.
Replying to an ancient (2021) thread which has already been merged...
I'd like to be able to use this facility for virtio devices.
Virtio already has a complicated relationship with the DMA API, because
there were a bunch of early VMM bugs where the virtio devices where
magically exempted from IOMMU protection, but the VMM lied to the guest
and claimed they weren't.
With the advent of confidential computing, and the VMM (or whatever's
emulating the virtio device) not being *allowed* to arbitrarily access
all of the guest's memory, the DMA API becomes necessary again.
Either a virtual IOMMU needs to determine which guest memory the VMM
may access, or the DMA API is wrappers around operations which
share/unshare (or unencrypt/encrypt) the memory in question.
All of which is complicated and slow, if we're looking at a minimal
privileged hypervisor stub like pKVM which enforces the lack of guest
memory access from VMM.
I'm thinking of defining a new type of virtio-pci device which cannot
do DMA to arbitrary system memory. Instead it has an additional memory
BAR which is used as a SWIOTLB for bounce buffering.
The driver for it would look much like the existing virtio-pci device
except that it would register the restricted-dma region first (and thus
the swiotlb dma_ops), and then just go through the rest of the setup
like any other virtio device.
That seems like it ought to be fairly simple, and seems like a
reasonable way to allow an untrusted VMM to provide virtio devices with
restricted DMA access.
While I start actually doing the typing... does anyone want to start
yelling at me now? Christoph? mst? :)
I don't mind as such (though I don't understand completely), but since
this is changing the device anyway, I am a bit confused why you can't
just set the VIRTIO_F_ACCESS_PLATFORM feature bit? This forces DMA API
which will DTRT for you, will it not?
That would be necessary but not sufficient. ...
could you explain pls?
My first cut at a proposed spec change looks something like this. I'll
post it to the virtio-comment list once I've done some corporate
bureaucracy and when the list stops sending me python tracebacks in
response to my subscribe request.
the linux foundation one does this? maybe poke at the admins.
quoted hunk
In the meantime I'll hack up some QEMU and guest Linux driver support
to match.
@@ -773,6 +773,9 @@ \chapter{Reserved Feature Bits}\label{sec:Reserved Feature Bits} Currently these device-independent feature bits are defined:\begin{description}+\item[VIRTIO_F_SWIOTLB (27)] This feature indicates that the device+ provides a memory region which is to be used for bounce buffering,+ rather than permitting direct memory access to system memory.\item[VIRTIO_F_INDIRECT_DESC (28)] Negotiating this feature indicates that the driver can use descriptors with the VIRTQ_DESC_F_INDIRECT flag set, as described in \ref{sec:Basic Facilities of a Virtio
@@ -885,6 +888,10 @@ \chapter{Reserved Feature Bits}\label{sec:Reserved Feature Bits} VIRTIO_F_ACCESS_PLATFORM is not offered, then a driver MUST pass only physical addresses to the device.+A driver SHOULD accept VIRTIO_F_SWIOTLB if it is offered, and it MUST+then pass only addresses within the Software IOTLB bounce buffer to the+device.+ A driver SHOULD accept VIRTIO_F_RING_PACKED if it is offered. A driver SHOULD accept VIRTIO_F_ORDER_PLATFORM if it is offered.
@@ -921,6 +928,10 @@ \chapter{Reserved Feature Bits}\label{sec:Reserved Feature Bits} A device MAY fail to operate further if VIRTIO_F_ACCESS_PLATFORM is not accepted.+A device MUST NOT offer VIRTIO_F_SWIOTLB if its transport does not+provide a Software IOTLB bounce buffer.+A device MAY fail to operate further if VIRTIO_F_SWIOTLB is not accepted.+ If VIRTIO_F_IN_ORDER has been negotiated, a device MUST use buffers in the same order in which they have been available.
@@ -129,6 +129,7 @@ \subsection{Virtio Structure PCI Capabilities}\label{sec:Virtio Transport Option\item ISR Status\item Device-specific configuration (optional)\item PCI configuration access+\item SWIOTLB bounce buffer\end{itemize} Each structure can be mapped by a Base Address register (BAR) belonging to
@@ -188,6 +189,8 @@ \subsection{Virtio Structure PCI Capabilities}\label{sec:Virtio Transport Option #define VIRTIO_PCI_CAP_SHARED_MEMORY_CFG 8 /* Vendor-specific data */ #define VIRTIO_PCI_CAP_VENDOR_CFG 9+/* Software IOTLB bounce buffer */+#define VIRTIO_PCI_CAP_SWIOTLB 10\end{lstlisting} Any other value is reserved for future use.
@@ -744,6 +747,36 @@ \subsubsection{Vendor data capability}\label{sec:Virtio The driver MUST qualify the \field{vendor_id} before interpreting or writing into the Vendor data capability.+\subsubsection{Software IOTLB bounce buffer capability}\label{sec:Virtio+Transport Options / Virtio Over PCI Bus / PCI Device Layout /+Software IOTLB bounce buffer capability}++The optional Software IOTLB bounce buffer capability allows the+device to provide a memory region which can be used by the driver+driver for bounce buffering. This allows a device on the PCI+transport to operate without DMA access to system memory addresses.++The Software IOTLB region is referenced by the+VIRTIO_PCI_CAP_SWIOTLB capability. Bus addresses within the referenced+range are not subject to the requirements of the VIRTIO_F_ORDER_PLATFORM+capability, if negotiated.
why not? an optimization?
A mix of swiotlb and system memory might be very challenging from POV
of ordering.
+
+\devicenormative{\paragraph}{Software IOTLB bounce buffer capability}{Virtio
+Transport Options / Virtio Over PCI Bus / PCI Device Layout /
+Software IOTLB bounce buffer capability}
+
+Devices which present the Software IOTLB bounce buffer capability
+SHOULD also offer the VIRTIO_F_SWIOTLB feature.
+
+\drivernormative{\paragraph}{Software IOTLB bounce buffer capability}{Virtio
+Transport Options / Virtio Over PCI Bus / PCI Device Layout /
+Software IOTLB bounce buffer capability}
+
+The driver SHOULD use the offered buffer in preference to passing system
+memory addresses to the device.
Even if not using VIRTIO_F_SWIOTLB? Is that really necessary?
If the driver accepts the VIRTIO_F_SWIOTLB
+feature, then the driver MUST use the offered buffer and never pass system
+memory addresses to the device.
+
\subsubsection{PCI configuration access capability}\label{sec:Virtio Transport Options / Virtio Over PCI Bus / PCI Device Layout / PCI configuration access capability}
The VIRTIO_PCI_CAP_PCI_CFG capability
From: David Woodhouse <dwmw2@infradead.org> Date: 2025-03-30 15:08:34
On Sun, 2025-03-30 at 09:42 -0400, Michael S. Tsirkin wrote:
On Fri, Mar 28, 2025 at 05:40:41PM +0000, David Woodhouse wrote:
quoted
On Fri, 2025-03-21 at 18:42 +0000, David Woodhouse wrote:
quoted
quoted
I don't mind as such (though I don't understand completely), but since
this is changing the device anyway, I am a bit confused why you can't
just set the VIRTIO_F_ACCESS_PLATFORM feature bit? This forces DMA API
which will DTRT for you, will it not?
My first cut at a proposed spec change looks something like this. I'll
post it to the virtio-comment list once I've done some corporate
bureaucracy and when the list stops sending me python tracebacks in
response to my subscribe request.
the linux foundation one does this? maybe poke at the admins.
quoted
In the meantime I'll hack up some QEMU and guest Linux driver support
to match.
Currently these device-independent feature bits are defined:
\begin{description}
+ \item[VIRTIO_F_SWIOTLB (27)] This feature indicates that the device
+ provides a memory region which is to be used for bounce buffering,
+ rather than permitting direct memory access to system memory.
\item[VIRTIO_F_INDIRECT_DESC (28)] Negotiating this feature indicates
that the driver can use descriptors with the VIRTQ_DESC_F_INDIRECT
flag set, as described in \ref{sec:Basic Facilities of a Virtio
VIRTIO_F_ACCESS_PLATFORM is not offered, then a driver MUST pass only physical
addresses to the device.
+A driver SHOULD accept VIRTIO_F_SWIOTLB if it is offered, and it MUST
+then pass only addresses within the Software IOTLB bounce buffer to the
+device.
+
A driver SHOULD accept VIRTIO_F_RING_PACKED if it is offered.
A driver SHOULD accept VIRTIO_F_ORDER_PLATFORM if it is offered.
A device MAY fail to operate further if VIRTIO_F_ACCESS_PLATFORM is not
accepted.
+A device MUST NOT offer VIRTIO_F_SWIOTLB if its transport does not
+provide a Software IOTLB bounce buffer.
+A device MAY fail to operate further if VIRTIO_F_SWIOTLB is not accepted.
+
If VIRTIO_F_IN_ORDER has been negotiated, a device MUST use
buffers in the same order in which they have been available.
@@ -129,6 +129,7 @@ \subsection{Virtio Structure PCI Capabilities}\label{sec:Virtio Transport Option
\item ISR Status
\item Device-specific configuration (optional)
\item PCI configuration access
+\item SWIOTLB bounce buffer
\end{itemize}
Each structure can be mapped by a Base Address register (BAR) belonging to
@@ -188,6 +189,8 @@ \subsection{Virtio Structure PCI Capabilities}\label{sec:Virtio Transport Option
#define VIRTIO_PCI_CAP_SHARED_MEMORY_CFG 8
/* Vendor-specific data */
#define VIRTIO_PCI_CAP_VENDOR_CFG 9
+/* Software IOTLB bounce buffer */
+#define VIRTIO_PCI_CAP_SWIOTLB 10
\end{lstlisting}
Any other value is reserved for future use.
@@ -744,6 +747,36 @@ \subsubsection{Vendor data capability}\label{sec:Virtio
The driver MUST qualify the \field{vendor_id} before
interpreting or writing into the Vendor data capability.
+\subsubsection{Software IOTLB bounce buffer capability}\label{sec:Virtio
+Transport Options / Virtio Over PCI Bus / PCI Device Layout /
+Software IOTLB bounce buffer capability}
+
+The optional Software IOTLB bounce buffer capability allows the
+device to provide a memory region which can be used by the driver
+driver for bounce buffering. This allows a device on the PCI
+transport to operate without DMA access to system memory addresses.
+
+The Software IOTLB region is referenced by the
+VIRTIO_PCI_CAP_SWIOTLB capability. Bus addresses within the referenced
+range are not subject to the requirements of the VIRTIO_F_ORDER_PLATFORM
+capability, if negotiated.
why not? an optimization?
A mix of swiotlb and system memory might be very challenging from POV
of ordering.
Conceptually, these addresses are *on* the PCI device. If the device is
accessing addresses which are local to it, they aren't subject to IOMMU
translation/filtering because they never even make it to the PCI bus as
memory transactions.
quoted
+
+\devicenormative{\paragraph}{Software IOTLB bounce buffer capability}{Virtio
+Transport Options / Virtio Over PCI Bus / PCI Device Layout /
+Software IOTLB bounce buffer capability}
+
+Devices which present the Software IOTLB bounce buffer capability
+SHOULD also offer the VIRTIO_F_SWIOTLB feature.
+
+\drivernormative{\paragraph}{Software IOTLB bounce buffer capability}{Virtio
+Transport Options / Virtio Over PCI Bus / PCI Device Layout /
+Software IOTLB bounce buffer capability}
+
+The driver SHOULD use the offered buffer in preference to passing system
+memory addresses to the device.
Even if not using VIRTIO_F_SWIOTLB? Is that really necessary?
That part isn't strictly necessary, but I think it makes sense, for
cases where the SWIOTLB support is an *optimisation* even if it isn't
strictly necessary.
Why might it be an "optimisation"? Well... if we're thinking of a model
like pKVM where the VMM can't just arbitrarily access guest memory,
using the SWIOTLB is a simple way to avoid that (by using the on-board
memory instead, which *can* be shared with the VMM).
But if we want to go to extra lengths to support unenlightened guests,
an implementation might choose to just *disable* the memory protection
if the guest doesn't negotiate VIRTIO_F_SWIOTLB, instead of breaking
that guest.
Or it might have a complicated emulation/snooping of virtqueues in the
trusted part of the hypervisor so that it knows which addresses the
guest has truly *asked* the VMM to access. (And yes, of course that's
what an IOMMU is for, but when have you seen hardware companies design
a two-stage IOMMU which supports actual PCI passthrough *and* get it
right for the hypervisor to 'snoop' on the stage1 page tables to
support emulated devices too....)
Ultimately I think it was natural to advertise the location of the
buffer with the VIRTIO_PCI_CAP_SWIOTLB capability and then to have the
separate VIRTIO_F_SWIOTLB for negotiation... leaving the obvious
question of what a device should do if it sees one but *not* the other.
Obviously you can't have VIRTIO_F_SWIOTLB *without* there actually
being a buffer advertised with VIRTIO_PCI_CAP_SWIOTLB (or its
equivalent for other transports). But the converse seemed reasonable as
a *hint* even if the use of the SWIOTLB isn't mandatory.
From: "Michael S. Tsirkin" <mst@redhat.com> Date: 2025-03-30 16:59:24
On Sun, Mar 30, 2025 at 04:07:56PM +0100, David Woodhouse wrote:
On Sun, 2025-03-30 at 09:42 -0400, Michael S. Tsirkin wrote:
quoted
On Fri, Mar 28, 2025 at 05:40:41PM +0000, David Woodhouse wrote:
quoted
On Fri, 2025-03-21 at 18:42 +0000, David Woodhouse wrote:
quoted
quoted
I don't mind as such (though I don't understand completely), but since
this is changing the device anyway, I am a bit confused why you can't
just set the VIRTIO_F_ACCESS_PLATFORM feature bit? This forces DMA API
which will DTRT for you, will it not?
My first cut at a proposed spec change looks something like this. I'll
post it to the virtio-comment list once I've done some corporate
bureaucracy and when the list stops sending me python tracebacks in
response to my subscribe request.
the linux foundation one does this? maybe poke at the admins.
quoted
In the meantime I'll hack up some QEMU and guest Linux driver support
to match.
Currently these device-independent feature bits are defined:
\begin{description}
+ \item[VIRTIO_F_SWIOTLB (27)] This feature indicates that the device
+ provides a memory region which is to be used for bounce buffering,
+ rather than permitting direct memory access to system memory.
\item[VIRTIO_F_INDIRECT_DESC (28)] Negotiating this feature indicates
that the driver can use descriptors with the VIRTQ_DESC_F_INDIRECT
flag set, as described in \ref{sec:Basic Facilities of a Virtio
VIRTIO_F_ACCESS_PLATFORM is not offered, then a driver MUST pass only physical
addresses to the device.
+A driver SHOULD accept VIRTIO_F_SWIOTLB if it is offered, and it MUST
+then pass only addresses within the Software IOTLB bounce buffer to the
+device.
+
A driver SHOULD accept VIRTIO_F_RING_PACKED if it is offered.
A driver SHOULD accept VIRTIO_F_ORDER_PLATFORM if it is offered.
A device MAY fail to operate further if VIRTIO_F_ACCESS_PLATFORM is not
accepted.
+A device MUST NOT offer VIRTIO_F_SWIOTLB if its transport does not
+provide a Software IOTLB bounce buffer.
+A device MAY fail to operate further if VIRTIO_F_SWIOTLB is not accepted.
+
If VIRTIO_F_IN_ORDER has been negotiated, a device MUST use
buffers in the same order in which they have been available.
@@ -129,6 +129,7 @@ \subsection{Virtio Structure PCI Capabilities}\label{sec:Virtio Transport Option
\item ISR Status
\item Device-specific configuration (optional)
\item PCI configuration access
+\item SWIOTLB bounce buffer
\end{itemize}
Each structure can be mapped by a Base Address register (BAR) belonging to
@@ -188,6 +189,8 @@ \subsection{Virtio Structure PCI Capabilities}\label{sec:Virtio Transport Option
#define VIRTIO_PCI_CAP_SHARED_MEMORY_CFG 8
/* Vendor-specific data */
#define VIRTIO_PCI_CAP_VENDOR_CFG 9
+/* Software IOTLB bounce buffer */
+#define VIRTIO_PCI_CAP_SWIOTLB 10
\end{lstlisting}
Any other value is reserved for future use.
@@ -744,6 +747,36 @@ \subsubsection{Vendor data capability}\label{sec:Virtio
The driver MUST qualify the \field{vendor_id} before
interpreting or writing into the Vendor data capability.
+\subsubsection{Software IOTLB bounce buffer capability}\label{sec:Virtio
+Transport Options / Virtio Over PCI Bus / PCI Device Layout /
+Software IOTLB bounce buffer capability}
+
+The optional Software IOTLB bounce buffer capability allows the
+device to provide a memory region which can be used by the driver
+driver for bounce buffering. This allows a device on the PCI
+transport to operate without DMA access to system memory addresses.
+
+The Software IOTLB region is referenced by the
+VIRTIO_PCI_CAP_SWIOTLB capability. Bus addresses within the referenced
+range are not subject to the requirements of the VIRTIO_F_ORDER_PLATFORM
+capability, if negotiated.
why not? an optimization?
A mix of swiotlb and system memory might be very challenging from POV
of ordering.
Conceptually, these addresses are *on* the PCI device. If the device is
accessing addresses which are local to it, they aren't subject to IOMMU
translation/filtering because they never even make it to the PCI bus as
memory transactions.
quoted
quoted
+
+\devicenormative{\paragraph}{Software IOTLB bounce buffer capability}{Virtio
+Transport Options / Virtio Over PCI Bus / PCI Device Layout /
+Software IOTLB bounce buffer capability}
+
+Devices which present the Software IOTLB bounce buffer capability
+SHOULD also offer the VIRTIO_F_SWIOTLB feature.
+
+\drivernormative{\paragraph}{Software IOTLB bounce buffer capability}{Virtio
+Transport Options / Virtio Over PCI Bus / PCI Device Layout /
+Software IOTLB bounce buffer capability}
+
+The driver SHOULD use the offered buffer in preference to passing system
+memory addresses to the device.
Even if not using VIRTIO_F_SWIOTLB? Is that really necessary?
That part isn't strictly necessary, but I think it makes sense, for
cases where the SWIOTLB support is an *optimisation* even if it isn't
strictly necessary.
Why might it be an "optimisation"? Well... if we're thinking of a model
like pKVM where the VMM can't just arbitrarily access guest memory,
using the SWIOTLB is a simple way to avoid that (by using the on-board
memory instead, which *can* be shared with the VMM).
But if we want to go to extra lengths to support unenlightened guests,
an implementation might choose to just *disable* the memory protection
if the guest doesn't negotiate VIRTIO_F_SWIOTLB, instead of breaking
that guest.
Or it might have a complicated emulation/snooping of virtqueues in the
trusted part of the hypervisor so that it knows which addresses the
guest has truly *asked* the VMM to access. (And yes, of course that's
what an IOMMU is for, but when have you seen hardware companies design
a two-stage IOMMU which supports actual PCI passthrough *and* get it
right for the hypervisor to 'snoop' on the stage1 page tables to
support emulated devices too....)
Ultimately I think it was natural to advertise the location of the
buffer with the VIRTIO_PCI_CAP_SWIOTLB capability and then to have the
separate VIRTIO_F_SWIOTLB for negotiation... leaving the obvious
question of what a device should do if it sees one but *not* the other.
Obviously you can't have VIRTIO_F_SWIOTLB *without* there actually
being a buffer advertised with VIRTIO_PCI_CAP_SWIOTLB (or its
equivalent for other transports). But the converse seemed reasonable as
a *hint* even if the use of the SWIOTLB isn't mandatory.
OK but I feel it's more work than you think, so we really need
a better reason than just "why not".
For example, it's not at all clear to me how the ordering is
going to work if buffers are in memory but the ring is swiotlb
or the reverse. Ordering will all be messed up.
--
MST
From: David Woodhouse <dwmw2@infradead.org> Date: 2025-03-30 20:08:45
On 30 March 2025 17:59:13 BST, "Michael S. Tsirkin" [off-list ref] wrote:
On Sun, Mar 30, 2025 at 04:07:56PM +0100, David Woodhouse wrote:
quoted
On Sun, 2025-03-30 at 09:42 -0400, Michael S. Tsirkin wrote:
quoted
On Fri, Mar 28, 2025 at 05:40:41PM +0000, David Woodhouse wrote:
quoted
On Fri, 2025-03-21 at 18:42 +0000, David Woodhouse wrote:
quoted
quoted
I don't mind as such (though I don't understand completely), but since
this is changing the device anyway, I am a bit confused why you can't
just set the VIRTIO_F_ACCESS_PLATFORM feature bit? This forces DMA API
which will DTRT for you, will it not?
My first cut at a proposed spec change looks something like this. I'll
post it to the virtio-comment list once I've done some corporate
bureaucracy and when the list stops sending me python tracebacks in
response to my subscribe request.
the linux foundation one does this? maybe poke at the admins.
quoted
In the meantime I'll hack up some QEMU and guest Linux driver support
to match.
Currently these device-independent feature bits are defined:
\begin{description}
+ \item[VIRTIO_F_SWIOTLB (27)] This feature indicates that the device
+ provides a memory region which is to be used for bounce buffering,
+ rather than permitting direct memory access to system memory.
\item[VIRTIO_F_INDIRECT_DESC (28)] Negotiating this feature indicates
that the driver can use descriptors with the VIRTQ_DESC_F_INDIRECT
flag set, as described in \ref{sec:Basic Facilities of a Virtio
VIRTIO_F_ACCESS_PLATFORM is not offered, then a driver MUST pass only physical
addresses to the device.
+A driver SHOULD accept VIRTIO_F_SWIOTLB if it is offered, and it MUST
+then pass only addresses within the Software IOTLB bounce buffer to the
+device.
+
A driver SHOULD accept VIRTIO_F_RING_PACKED if it is offered.
A driver SHOULD accept VIRTIO_F_ORDER_PLATFORM if it is offered.
A device MAY fail to operate further if VIRTIO_F_ACCESS_PLATFORM is not
accepted.
+A device MUST NOT offer VIRTIO_F_SWIOTLB if its transport does not
+provide a Software IOTLB bounce buffer.
+A device MAY fail to operate further if VIRTIO_F_SWIOTLB is not accepted.
+
If VIRTIO_F_IN_ORDER has been negotiated, a device MUST use
buffers in the same order in which they have been available.
@@ -129,6 +129,7 @@ \subsection{Virtio Structure PCI Capabilities}\label{sec:Virtio Transport Option
\item ISR Status
\item Device-specific configuration (optional)
\item PCI configuration access
+\item SWIOTLB bounce buffer
\end{itemize}
Each structure can be mapped by a Base Address register (BAR) belonging to
@@ -188,6 +189,8 @@ \subsection{Virtio Structure PCI Capabilities}\label{sec:Virtio Transport Option
#define VIRTIO_PCI_CAP_SHARED_MEMORY_CFG 8
/* Vendor-specific data */
#define VIRTIO_PCI_CAP_VENDOR_CFG 9
+/* Software IOTLB bounce buffer */
+#define VIRTIO_PCI_CAP_SWIOTLB 10
\end{lstlisting}
Any other value is reserved for future use.
@@ -744,6 +747,36 @@ \subsubsection{Vendor data capability}\label{sec:Virtio
The driver MUST qualify the \field{vendor_id} before
interpreting or writing into the Vendor data capability.
+\subsubsection{Software IOTLB bounce buffer capability}\label{sec:Virtio
+Transport Options / Virtio Over PCI Bus / PCI Device Layout /
+Software IOTLB bounce buffer capability}
+
+The optional Software IOTLB bounce buffer capability allows the
+device to provide a memory region which can be used by the driver
+driver for bounce buffering. This allows a device on the PCI
+transport to operate without DMA access to system memory addresses.
+
+The Software IOTLB region is referenced by the
+VIRTIO_PCI_CAP_SWIOTLB capability. Bus addresses within the referenced
+range are not subject to the requirements of the VIRTIO_F_ORDER_PLATFORM
+capability, if negotiated.
why not? an optimization?
A mix of swiotlb and system memory might be very challenging from POV
of ordering.
Conceptually, these addresses are *on* the PCI device. If the device is
accessing addresses which are local to it, they aren't subject to IOMMU
translation/filtering because they never even make it to the PCI bus as
memory transactions.
quoted
quoted
+
+\devicenormative{\paragraph}{Software IOTLB bounce buffer capability}{Virtio
+Transport Options / Virtio Over PCI Bus / PCI Device Layout /
+Software IOTLB bounce buffer capability}
+
+Devices which present the Software IOTLB bounce buffer capability
+SHOULD also offer the VIRTIO_F_SWIOTLB feature.
+
+\drivernormative{\paragraph}{Software IOTLB bounce buffer capability}{Virtio
+Transport Options / Virtio Over PCI Bus / PCI Device Layout /
+Software IOTLB bounce buffer capability}
+
+The driver SHOULD use the offered buffer in preference to passing system
+memory addresses to the device.
Even if not using VIRTIO_F_SWIOTLB? Is that really necessary?
That part isn't strictly necessary, but I think it makes sense, for
cases where the SWIOTLB support is an *optimisation* even if it isn't
strictly necessary.
Why might it be an "optimisation"? Well... if we're thinking of a model
like pKVM where the VMM can't just arbitrarily access guest memory,
using the SWIOTLB is a simple way to avoid that (by using the on-board
memory instead, which *can* be shared with the VMM).
But if we want to go to extra lengths to support unenlightened guests,
an implementation might choose to just *disable* the memory protection
if the guest doesn't negotiate VIRTIO_F_SWIOTLB, instead of breaking
that guest.
Or it might have a complicated emulation/snooping of virtqueues in the
trusted part of the hypervisor so that it knows which addresses the
guest has truly *asked* the VMM to access. (And yes, of course that's
what an IOMMU is for, but when have you seen hardware companies design
a two-stage IOMMU which supports actual PCI passthrough *and* get it
right for the hypervisor to 'snoop' on the stage1 page tables to
support emulated devices too....)
Ultimately I think it was natural to advertise the location of the
buffer with the VIRTIO_PCI_CAP_SWIOTLB capability and then to have the
separate VIRTIO_F_SWIOTLB for negotiation... leaving the obvious
question of what a device should do if it sees one but *not* the other.
Obviously you can't have VIRTIO_F_SWIOTLB *without* there actually
being a buffer advertised with VIRTIO_PCI_CAP_SWIOTLB (or its
equivalent for other transports). But the converse seemed reasonable as
a *hint* even if the use of the SWIOTLB isn't mandatory.
OK but I feel it's more work than you think, so we really need
a better reason than just "why not".
For example, it's not at all clear to me how the ordering is
going to work if buffers are in memory but the ring is swiotlb
or the reverse. Ordering will all be messed up.
Maybe. Although by the time the driver has *observed* the data written to the swiotlb on the device's BAR, it has had to cross the same PCI bus.
But sure, we could require all-or-nothing. Or require that the SWIOTLB only be used if the driver negotiates VIRTIO_F_SWIOTLB.
Even in the latter case we can still allow for SWIOTLB to either be a requirement or a hint, purely down to whether the device *allows* the driver not to negotiate `VIRTIO_F_SWIOTLB`.
From: "Michael S. Tsirkin" <mst@redhat.com> Date: 2025-03-30 17:06:57
On Fri, Mar 21, 2025 at 06:42:20PM +0000, David Woodhouse wrote:
On Fri, 2025-03-21 at 14:32 -0400, Michael S. Tsirkin wrote:
quoted
On Fri, Mar 21, 2025 at 03:38:10PM +0000, David Woodhouse wrote:
quoted
On Tue, 2021-02-09 at 14:21 +0800, Claire Chang wrote:
quoted
This series implements mitigations for lack of DMA access control on
systems without an IOMMU, which could result in the DMA accessing the
system memory at unexpected times and/or unexpected addresses, possibly
leading to data leakage or corruption.
Replying to an ancient (2021) thread which has already been merged...
I'd like to be able to use this facility for virtio devices.
Virtio already has a complicated relationship with the DMA API, because
there were a bunch of early VMM bugs where the virtio devices where
magically exempted from IOMMU protection, but the VMM lied to the guest
and claimed they weren't.
With the advent of confidential computing, and the VMM (or whatever's
emulating the virtio device) not being *allowed* to arbitrarily access
all of the guest's memory, the DMA API becomes necessary again.
Either a virtual IOMMU needs to determine which guest memory the VMM
may access, or the DMA API is wrappers around operations which
share/unshare (or unencrypt/encrypt) the memory in question.
All of which is complicated and slow, if we're looking at a minimal
privileged hypervisor stub like pKVM which enforces the lack of guest
memory access from VMM.
I'm thinking of defining a new type of virtio-pci device which cannot
do DMA to arbitrary system memory. Instead it has an additional memory
BAR which is used as a SWIOTLB for bounce buffering.
The driver for it would look much like the existing virtio-pci device
except that it would register the restricted-dma region first (and thus
the swiotlb dma_ops), and then just go through the rest of the setup
like any other virtio device.
That seems like it ought to be fairly simple, and seems like a
reasonable way to allow an untrusted VMM to provide virtio devices with
restricted DMA access.
While I start actually doing the typing... does anyone want to start
yelling at me now? Christoph? mst? :)
I don't mind as such (though I don't understand completely), but since
this is changing the device anyway, I am a bit confused why you can't
just set the VIRTIO_F_ACCESS_PLATFORM feature bit? This forces DMA API
which will DTRT for you, will it not?
That would be necessary but not sufficient. The question is *what* does
the DMA API do?
For a real passthrough PCI device, perhaps we'd have a vIOMMU exposed
to the guest so that it can do real protection with two-stage page
tables (IOVA→GPA under control of the guest, GPA→HPA under control of
the hypervisor). For that to work in the pKVM model though, you'd need
pKVM to be talking the guest's stage1 I/O page tables to see if a given
access from the VMM ought to be permitted?
Or for confidential guests there could be DMA ops which are an
'enlightenment'; a hypercall into pKVM to share/unshare pages so that
the VMM can actually access them, or SEV-SNP guests might mark pages
unencrypted to have the same effect with hardware protection.
Doing any of those dynamically to allow the VMM to access buffers in
arbitrary guest memory (when it wouldn't normally have access to
arbitrary guest memory) is complex and doesn't perform very well. And
exposes a full 4KiB page for any byte that needs to be made available.
Thus the idea of having a fixed range of memory to use for a SWIOTLB,
which is fairly much what the restricted DMA setup is all about.
We're just proposing that we build it in to a virtio-pci device model,
which automatically uses the extra memory BAR instead of the
restricted-dma-pool DT node.
It's basically just allowing us to expose through PCI, what I believe
we can already do for virtio in DT.
I am not saying I am against this extension.
The idea to restrict DMA has a lot of merit outside pkvm.
For example, with a physical devices, limiting its DMA
to a fixed range can be good for security at a cost of
an extra data copy.
So I am not saying we have to block this specific hack.
what worries me fundamentally is I am not sure it works well
e.g. for physical virtio cards.
Attempts to pass data between devices will now also require
extra data copies.
Did you think about adding an swiotlb mode to virtio-iommu at all?
Much easier than parsing page tables.
--
MST
From: David Woodhouse <dwmw2@infradead.org> Date: 2025-03-30 21:28:36
On 30 March 2025 18:06:47 BST, "Michael S. Tsirkin" [off-list ref] wrote:
quoted
It's basically just allowing us to expose through PCI, what I believe
we can already do for virtio in DT.
I am not saying I am against this extension.
The idea to restrict DMA has a lot of merit outside pkvm.
For example, with a physical devices, limiting its DMA
to a fixed range can be good for security at a cost of
an extra data copy.
So I am not saying we have to block this specific hack.
what worries me fundamentally is I am not sure it works well
e.g. for physical virtio cards.
Not sure why it doesn't work for physical cards. They don't need to be bus-mastering; they just take data from a buffer in their own RAM.
Attempts to pass data between devices will now also require
extra data copies.
Yes. I think that's acceptable, but if we really cared we could perhaps extend the capability to refer to a range inside a given BAR on a specific *device*? Or maybe just *function*, and allow sharing of SWIOTLB buffer within a multi-function device?
I think it's overkill though.
Did you think about adding an swiotlb mode to virtio-iommu at all?
Much easier than parsing page tables.
Often the guests which need this will have a real IOMMU for the true pass-through devices. Adding a virtio-iommu into the mix (or any other system-wide way of doing something different for certain devices) is problematic.
The on-device buffer keeps it nice and simple, and even allows us to do device support for operating systems like Windows where it's a lot harder to do anything generic in the core OS.
From: "Michael S. Tsirkin" <mst@redhat.com> Date: 2025-03-30 21:48:53
On Sun, Mar 30, 2025 at 10:27:58PM +0100, David Woodhouse wrote:
On 30 March 2025 18:06:47 BST, "Michael S. Tsirkin" [off-list ref] wrote:
quoted
quoted
It's basically just allowing us to expose through PCI, what I believe
we can already do for virtio in DT.
I am not saying I am against this extension.
The idea to restrict DMA has a lot of merit outside pkvm.
For example, with a physical devices, limiting its DMA
to a fixed range can be good for security at a cost of
an extra data copy.
So I am not saying we have to block this specific hack.
what worries me fundamentally is I am not sure it works well
e.g. for physical virtio cards.
Not sure why it doesn't work for physical cards. They don't need to be bus-mastering; they just take data from a buffer in their own RAM.
I mean, it kind of does, it is just that CPU pulling data over the PCI bus
stalls it so is very expensive. It is not by chance people switched to
DMA almost exclusively.
quoted
Attempts to pass data between devices will now also require
extra data copies.
Yes. I think that's acceptable, but if we really cared we could perhaps extend the capability to refer to a range inside a given BAR on a specific *device*? Or maybe just *function*, and allow sharing of SWIOTLB buffer within a multi-function device?
Fundamentally, this is what dmabuf does.
I think it's overkill though.
quoted
Did you think about adding an swiotlb mode to virtio-iommu at all?
Much easier than parsing page tables.
Often the guests which need this will have a real IOMMU for the true
pass-through devices.
Not sure I understand. You mean with things like stage 2 passthrough?
Adding a virtio-iommu into the mix (or any other
system-wide way of doing something different for certain devices) is
problematic.
OK... but the issue isn't specific to no DMA devices, is it?
The on-device buffer keeps it nice and simple,
I am not saying it is not.
It's just a little boutique.
and even allows us to
do device support for operating systems like Windows where it's a lot
harder to do anything generic in the core OS.
Well we do need virtio iommu windows support sooner or later, anyway.
--
MST
From: David Woodhouse <dwmw2@infradead.org> Date: 2025-03-31 09:42:55
On Sun, 2025-03-30 at 17:48 -0400, Michael S. Tsirkin wrote:
On Sun, Mar 30, 2025 at 10:27:58PM +0100, David Woodhouse wrote:
quoted
On 30 March 2025 18:06:47 BST, "Michael S. Tsirkin" [off-list ref] wrote:
quoted
quoted
It's basically just allowing us to expose through PCI, what I believe
we can already do for virtio in DT.
I am not saying I am against this extension.
The idea to restrict DMA has a lot of merit outside pkvm.
For example, with a physical devices, limiting its DMA
to a fixed range can be good for security at a cost of
an extra data copy.
So I am not saying we have to block this specific hack.
what worries me fundamentally is I am not sure it works well
e.g. for physical virtio cards.
Not sure why it doesn't work for physical cards. They don't need to
be bus-mastering; they just take data from a buffer in their own
RAM.
I mean, it kind of does, it is just that CPU pulling data over the PCI bus
stalls it so is very expensive. It is not by chance people switched to
DMA almost exclusively.
Yes. For a physical implementation it would not be the most high-
performance option... unless DMA is somehow blocked as it is in the
pKVM+virt case.
In the case of a virtual implementation, however, the performance is
not an issue because it'll be backed by host memory anyway. (It's just
that because it's presented to the guest and the trusted part of the
hypervisor as PCI BAR space instead of main memory, it's a whole lot
more practical to deal with the fact that it's *shared* with the VMM.)
quoted
quoted
Attempts to pass data between devices will now also require
extra data copies.
Yes. I think that's acceptable, but if we really cared we could
perhaps extend the capability to refer to a range inside a given
BAR on a specific *device*? Or maybe just *function*, and allow
sharing of SWIOTLB buffer within a multi-function device?
Fundamentally, this is what dmabuf does.
In software, yes. Extending it to hardware is a little harder.
In principle, it might be quite nice to offer a single SWIOTLB buffer
region (in a BAR of one device) and have multiple virtio devices share
it. Not just because of passing data between devices, as you mentioned,
but also because it'll be a more efficient use of memory than each
device having its own buffer and allocation pool.
So how would a device indicate that it can use a SWIOTLB buffer which
is in a BAR of a *different* device?
Not by physical address, because BARs get moved around.
Not even by PCI bus/dev/fn/BAR# because *buses* get renumbered.
You could limit it to sharing within one PCI "bus", and use just
dev/fn/BAR#? Or even within one PCI device and just fn/BAR#? The latter
could theoretically be usable by multi-function physical devices.
The standard struct virtio_pci_cap (which I used for
VIRTIO_PCI_CAP_SWIOTLB) just contains BAR and offset/length. We could
extend it with device + function, using -1 for 'self', to allow for
such sharing?
Still not convinced it isn't overkill, but it's certainly easy enough
to add on the *spec* side. I haven't yet looked at how that sharing
would work in Linux on the guest side; thus far what I'm proposing is
intended to be almost identical to the per-device thing that should
already work with a `restricted-dma-pool' node in device-tree.
quoted
I think it's overkill though.
quoted
Did you think about adding an swiotlb mode to virtio-iommu at all?
Much easier than parsing page tables.
Often the guests which need this will have a real IOMMU for the true
pass-through devices.
Not sure I understand. You mean with things like stage 2 passthrough?
Yes. AMD's latest IOMMU spec documents it, for example. Exposing a
'vIOMMU' to the guest which handles just stage 1 (IOVA→GPA) while the
hypervisor controls the normal GPA→HPA translation in stage 2.
Then the guest gets an accelerated path *directly* to the hardware for
its IOTLB flushes... which means the hypervisor doesn't get to *see*
those IOTLB flushes so it's a PITA to do device emulation as if it's
covered by that same IOMMU.
(Actually I haven't checked the AMD one in detail for that flaw; most
*other* 2-stage IOMMUs I've seen do have it, and I *bet* AMD does too).
quoted
Adding a virtio-iommu into the mix (or any other
system-wide way of doing something different for certain devices) is
problematic.
OK... but the issue isn't specific to no DMA devices, is it?
Hm? Allowing virtio devices to operate as "no-DMA devices" is a
*workaround* for the issue.
The issue is that the VMM may not have full access to the guest's
memory for emulating devices. These days, virtio covers a large
proportion of emulated devices.
So I do think the issue is fairly specific to virtio devices, and
suspect that's what you meant to type above?
We pondered teaching the trusted part of the hypervisor (e.g. pKVM) to
snoop on virtqueues enough to 'know' which memory the VMM was genuinely
being *invited* to read/write... and we ran away screaming. (In order
to have sufficient trust, you end up not just snooping but implementing
quite a lot of the emulation on the trusted side. And then complex
enlightenments in the VMM and the untrusted Linux/KVM which hosts it,
to interact with that.)
Then we realised that for existing DT guests it's trivial just to add
the `restricted-dma-pool` node. And wanted to do the same for the
guests who are afflicted with UEFI/ACPI too. So here we are, trying to
add the same capability to virtio-pci.
quoted
The on-device buffer keeps it nice and simple,
I am not saying it is not.
It's just a little boutique.
Fair. Although with the advent of confidential computing and
restrictions on guest memory access, perhaps becoming less boutique
over time?
And it should also be fairly low-friction; it's a whole lot cleaner in
the spec than the awful VIRTIO_F_ACCESS_PLATFORM legacy, and even in
the Linux guest driver it should work fairly simply given the existing
restricted-dma support (although of course that shouldn't entirely be
our guiding motivation).
quoted
and even allows us to
do device support for operating systems like Windows where it's a lot
harder to do anything generic in the core OS.
Well we do need virtio iommu windows support sooner or later, anyway.
Heh, good luck with that :)
And actually, doesn't that only support *DMA* remapping? So you still
wouldn't be able to boot a Windows guest with >255 vCPUs without some
further enlightenment (like Windows guests finally supporting the 15-
bit MSI extension that even Hyper-V supports on the host side...)