[PATCH 1/5] clk: rockchip: add clock ids for PCLK_DPHYRX and PCLK_DPHYTX0 on rk3368

Subsystems: common clk framework, open firmware and flattened device tree bindings, the rest

STALE2040d LANDED

Landed in mainline as 0be10b6f68b2 on 2021-02-06.

6 messages, 1 author, 2021-02-06 · open the first message on its own page

[PATCH 1/5] clk: rockchip: add clock ids for PCLK_DPHYRX and PCLK_DPHYTX0 on rk3368

From: Heiko Stuebner <heiko@sntech.de>
Date: 2021-02-06 00:32:45

From: Heiko Stuebner <redacted>

Needed by the mipi dphys.
The naming follows the clock names in the manual.

Signed-off-by: Heiko Stuebner <redacted>
---
 include/dt-bindings/clock/rk3368-cru.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/dt-bindings/clock/rk3368-cru.h b/include/dt-bindings/clock/rk3368-cru.h
index 0a06c5f514d7..f89683295935 100644
--- a/include/dt-bindings/clock/rk3368-cru.h
+++ b/include/dt-bindings/clock/rk3368-cru.h

@@ -148,6 +148,8 @@
 #define PCLK_VIP		367
 #define PCLK_WDT		368
 #define PCLK_EFUSE256		369
+#define PCLK_DPHYRX		370
+#define PCLK_DPHYTX0		371
 
 /* hclk gates */
 #define HCLK_SFC		448

-- 
2.29.2

[PATCH 2/5] clk: rockchip: use clock ids for PCLK_DPHYRX and PCLK_DPHYTX0 on rk3368

From: Heiko Stuebner <heiko@sntech.de>
Date: 2021-02-05 11:08:42

From: Heiko Stuebner <redacted>

Export the clocks via the newly added clock-ids.

Signed-off-by: Heiko Stuebner <redacted>
---
 drivers/clk/rockchip/clk-rk3368.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/rockchip/clk-rk3368.c b/drivers/clk/rockchip/clk-rk3368.c
index 55443349439b..76fb04120089 100644
--- a/drivers/clk/rockchip/clk-rk3368.c
+++ b/drivers/clk/rockchip/clk-rk3368.c

@@ -818,8 +818,8 @@ static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = {
 	 * pclk_vio gates
 	 * pclk_vio comes from the exactly same source as hclk_vio
 	 */
-	GATE(0, "pclk_dphyrx", "hclk_vio", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(14), 8, GFLAGS),
-	GATE(0, "pclk_dphytx", "hclk_vio", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(14), 8, GFLAGS),
+	GATE(PCLK_DPHYRX, "pclk_dphyrx", "hclk_vio", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(14), 8, GFLAGS),
+	GATE(PCLK_DPHYTX0, "pclk_dphytx0", "hclk_vio", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(14), 8, GFLAGS),
 
 	/* pclk_pd_pmu gates */
 	GATE(PCLK_PMUGRF, "pclk_pmugrf", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(23), 5, GFLAGS),

-- 
2.29.2

[PATCH 5/5] clk: rockchip: fix DPHY gate locations on rk3368

From: Heiko Stuebner <heiko@sntech.de>
Date: 2021-02-05 11:09:25

From: Heiko Stuebner <redacted>

Fix the register and bits of the DPHY gate locations.

Signed-off-by: Heiko Stuebner <redacted>
---
 drivers/clk/rockchip/clk-rk3368.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/rockchip/clk-rk3368.c b/drivers/clk/rockchip/clk-rk3368.c
index 61413be48d1a..9a0dab9448db 100644
--- a/drivers/clk/rockchip/clk-rk3368.c
+++ b/drivers/clk/rockchip/clk-rk3368.c

@@ -818,8 +818,8 @@ static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = {
 	 * pclk_vio gates
 	 * pclk_vio comes from the exactly same source as hclk_vio
 	 */
-	GATE(PCLK_DPHYRX, "pclk_dphyrx", "hclk_vio", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(14), 8, GFLAGS),
-	GATE(PCLK_DPHYTX0, "pclk_dphytx0", "hclk_vio", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(14), 8, GFLAGS),
+	GATE(PCLK_DPHYRX, "pclk_dphyrx", "hclk_vio", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(22), 11, GFLAGS),
+	GATE(PCLK_DPHYTX0, "pclk_dphytx0", "hclk_vio", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(22), 10, GFLAGS),
 
 	/* pclk_pd_pmu gates */
 	GATE(PCLK_PMUGRF, "pclk_pmugrf", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(23), 5, GFLAGS),

-- 
2.29.2

[PATCH 3/5] clk: rockchip: add clock id for SCLK_VIP_OUT on rk3368

From: Heiko Stuebner <heiko@sntech.de>
Date: 2021-02-06 00:33:38

From: Heiko Stuebner <redacted>

Needed to provide clocks for cameras.

Signed-off-by: Heiko Stuebner <redacted>
---
 include/dt-bindings/clock/rk3368-cru.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/dt-bindings/clock/rk3368-cru.h b/include/dt-bindings/clock/rk3368-cru.h
index f89683295935..83c72a163fd3 100644
--- a/include/dt-bindings/clock/rk3368-cru.h
+++ b/include/dt-bindings/clock/rk3368-cru.h

@@ -78,6 +78,7 @@
 #define SCLK_TIMER13		136
 #define SCLK_TIMER14		137
 #define SCLK_TIMER15		138
+#define SCLK_VIP_OUT		139
 
 #define DCLK_VOP		190
 #define MCLK_CRYPTO		191

-- 
2.29.2

[PATCH 4/5] clk: rockchip: use clock id for SCLK_VIP_OUT on rk3368

From: Heiko Stuebner <heiko@sntech.de>
Date: 2021-02-06 00:33:59

From: Heiko Stuebner <redacted>

Export the vip-out clock via the newly added clock-id.

Signed-off-by: Heiko Stuebner <redacted>
---
 drivers/clk/rockchip/clk-rk3368.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/rockchip/clk-rk3368.c b/drivers/clk/rockchip/clk-rk3368.c
index 76fb04120089..61413be48d1a 100644
--- a/drivers/clk/rockchip/clk-rk3368.c
+++ b/drivers/clk/rockchip/clk-rk3368.c

@@ -474,7 +474,7 @@ static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = {
 	COMPOSITE_NODIV(0, "vip_src", mux_pll_src_cpll_gpll_p, 0,
 			RK3368_CLKSEL_CON(21), 15, 1, MFLAGS,
 			RK3368_CLKGATE_CON(4), 5, GFLAGS),
-	COMPOSITE_NOGATE(0, "sclk_vip_out", mux_vip_out_p, 0,
+	COMPOSITE_NOGATE(SCLK_VIP_OUT, "sclk_vip_out", mux_vip_out_p, 0,
 			RK3368_CLKSEL_CON(21), 14, 1, MFLAGS, 8, 5, DFLAGS),
 
 	COMPOSITE_NODIV(SCLK_EDP_24M, "sclk_edp_24m", mux_edp_24m_p, 0,

-- 
2.29.2

Re: [PATCH 1/5] clk: rockchip: add clock ids for PCLK_DPHYRX and PCLK_DPHYTX0 on rk3368

From: Heiko Stuebner <heiko@sntech.de>
Date: 2021-02-06 05:06:40

On Fri, 5 Feb 2021 12:04:58 +0100, Heiko Stuebner wrote:

Needed by the mipi dphys.
The naming follows the clock names in the manual.

Applied, thanks!

[1/5] clk: rockchip: add clock ids for PCLK_DPHYRX and PCLK_DPHYTX0 on rk3368
      commit: 0be10b6f68b217876665031f643e571a5661fc9c
[2/5] clk: rockchip: use clock ids for PCLK_DPHYRX and PCLK_DPHYTX0 on rk3368
      commit: fabb841c5b16721298cfe649b569a4fa40af28a6
[3/5] clk: rockchip: add clock id for SCLK_VIP_OUT on rk3368
      commit: 686458aa752362f86d881d7fa4576c9f175b2d9b
[4/5] clk: rockchip: use clock id for SCLK_VIP_OUT on rk3368
      commit: ed2243e0038b8afdd7726d117da34ee4577e11ad
[5/5] clk: rockchip: fix DPHY gate locations on rk3368
      commit: 4bc23b3c83c9a3fc0a7dd8f2f11f451aa92c85cd

Best regards,
-- 
Heiko Stuebner [off-list ref]

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