[PATCH v2 0/4] arm: dts: Aspeed SoC device-tree update

This series fixes a few things in some Aspeed BMC device trees:

 - Fix an error in a memory reserve address on Romulus systems
 - Update AST2400 and AST2500 device-trees to add a label to the
   SRAM node and add the coprocessor interrupts controller node
   along with a binding.

The reserved memory for the VGA frame buffer is at the wrong address
for this system.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
---
 arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts b/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts
index 0b9b37d4d6ef..7d28c03a9e0b 100644
--- a/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts

@@ -21,9 +21,9 @@
 		#size-cells = <1>;
 		ranges;
 
-		vga_memory: framebuffer@bf000000 {
+		vga_memory: framebuffer@9f000000 {
 			no-map;
-			reg = <0xbf000000 0x01000000>; /* 16M */
+			reg = <0x9f000000 0x01000000>; /* 16M */
 		};
 
 		flash_memory: region@98000000 {

-- 
2.17.1

Add the device-tree binding definition for the AST2400
and AST2500 coprocessor interrupt controller

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
 .../devicetree/bindings/misc/aspeed,cvic.txt  | 35 +++++++++++++++++++
 1 file changed, 35 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/misc/aspeed,cvic.txt

diff --git a/Documentation/devicetree/bindings/misc/aspeed,cvic.txt b/Documentation/devicetree/bindings/misc/aspeed,cvic.txt
new file mode 100644
index 000000000000..2562e2991e4d
--- /dev/null
+++ b/Documentation/devicetree/bindings/misc/aspeed,cvic.txt

@@ -0,0 +1,35 @@
+* Aspeed AST2400 and AST2500 coprocessor interrupt controller
+
+This file describes the bindings for the interrupt controller present
+in the AST2400 and AST2500 BMC SoCs which provides interrupt to the
+ColdFire coprocessor.
+
+It is not a normal interrupt controller and it would be rather
+inconvenient to create an interrupt tree for it as it somewhat shares
+some of the same sources as the main ARM interrupt controller but with
+different numbers.
+
+The AST2500 supports a SW generated interrupt
+
+Required properties:
+- reg: address and length of the register for the device.
+- compatible: "aspeed,cvic" and one of:
+		"aspeed,ast2400-cvic"
+	      or
+		"aspeed,ast2500-cvic"
+
+- valid-sources: One cell, bitmap of supported sources for the implementation
+
+Optional properties;
+- copro-sw-interrupts: List of interrupt numbers that can be used as
+		       SW interrupts from the ARM to the coprocessor.
+		       (AST2500 only)
+
+Example:
+
+	cvic: copro-interrupt-controller@1e6c2000 {
+		compatible = "aspeed,ast2500-cvic";
+		valid-sources = <0xffffffff>;
+		copro-sw-interrupts = <1>;
+		reg = <0x1e6c2000 0x80>;
+	};

-- 
2.17.1

Add the missing node for the CVIC (the coprocessor interrupt
controller) and add a label to the SRAM node so it can be
referenced from the board device-tree file.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
 arch/arm/boot/dts/aspeed-g5.dtsi | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
index 17f2714d18a7..21141ca1bfa4 100644
--- a/arch/arm/boot/dts/aspeed-g5.dtsi
+++ b/arch/arm/boot/dts/aspeed-g5.dtsi

@@ -127,6 +127,13 @@
 			reg = <0x1e6c0080 0x80>;
 		};
 
+		cvic: copro-interrupt-controller@1e6c2000 {
+			compatible = "aspeed,ast2500-cvic", "aspeed-cvic";
+			valid-sources = <0xffffffff>;
+			copro-sw-interrupts = <1>;
+			reg = <0x1e6c2000 0x80>;
+		};
+
 		mac0: ethernet@1e660000 {
 			compatible = "aspeed,ast2500-mac", "faraday,ftgmac100";
 			reg = <0x1e660000 0x180>;

@@ -211,7 +218,7 @@
 				status = "disabled";
 			};
 
-			sram@1e720000 {
+			sram: sram@1e720000 {
 				compatible = "mmio-sram";
 				reg = <0x1e720000 0x9000>;	// 36K
 			};

-- 
2.17.1

Add the missing node for the CVIC (the coprocessor interrupt
controller) and add a label to the SRAM node so it can be
referenced from the board device-tree file.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
 arch/arm/boot/dts/aspeed-g4.dtsi | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
index 75df1573380e..b1a19f99a4c9 100644
--- a/arch/arm/boot/dts/aspeed-g4.dtsi
+++ b/arch/arm/boot/dts/aspeed-g4.dtsi

@@ -92,6 +92,12 @@
 			reg = <0x1e6c0080 0x80>;
 		};
 
+		cvic: copro-interrupt-controller@1e6c2000 {
+			compatible = "aspeed,ast2400-cvic", "aspeed-cvic";
+			valid-sources = <0x7fffffff>;
+			reg = <0x1e6c2000 0x80>;
+		};
+
 		mac0: ethernet@1e660000 {
 			compatible = "aspeed,ast2400-mac", "faraday,ftgmac100";
 			reg = <0x1e660000 0x180>;

@@ -161,7 +167,7 @@
 				status = "disabled";
 			};
 
-			sram@1e720000 {
+			sram: sram@1e720000 {
 				compatible = "mmio-sram";
 				reg = <0x1e720000 0x8000>;	// 32K
 			};

-- 
2.17.1

On Mon, 2018-06-18 at 14:58 +1000, Benjamin Herrenschmidt wrote:

The reserved memory for the VGA frame buffer is at the wrong address
for this system.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>

Note: These are pre-reqs for subsequent work, so if they are accepted,
I will put them in the fsi tree that I send to Greg (though it can also
be in an ARM soc tree).

Let me know if you prefer that I create a topic branch to pull on both
sides on k.org

On 18 June 2018 at 14:29, Benjamin Herrenschmidt
[off-list ref] wrote:

Is there a reason you didn't put this in bindings/interrupt-controller?

Aside from that this looks good.

On Tue, 2018-06-19 at 16:26 +0930, Joel Stanley wrote:

On 18 June 2018 at 14:29, Benjamin Herrenschmidt
[off-list ref] wrote:

quoted

Add the device-tree binding definition for the AST2400
and AST2500 coprocessor interrupt controller

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
 .../devicetree/bindings/misc/aspeed,cvic.txt  | 35 +++++++++++++++++++
 1 file changed, 35 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/misc/aspeed,cvic.txt

diff --git a/Documentation/devicetree/bindings/misc/aspeed,cvic.txt b/Documentation/devicetree/bindings/misc/aspeed,cvic.txt
new file mode 100644
index 000000000000..2562e2991e4d
--- /dev/null
+++ b/Documentation/devicetree/bindings/misc/aspeed,cvic.txt

Is there a reason you didn't put this in bindings/interrupt-controller?

Well, I don't call it interrupt-controller anymore, it's not an
interrupt controller for the main CPU so I decided to leave it out.

If you (or somebody) has strong feeling about it, I can call it
interrupt-controller again and move it back there :)

Aside from that this looks good.

quoted

@@ -0,0 +1,35 @@
+* Aspeed AST2400 and AST2500 coprocessor interrupt controller
+
+This file describes the bindings for the interrupt controller present
+in the AST2400 and AST2500 BMC SoCs which provides interrupt to the
+ColdFire coprocessor.
+
+It is not a normal interrupt controller and it would be rather
+inconvenient to create an interrupt tree for it as it somewhat shares
+some of the same sources as the main ARM interrupt controller but with
+different numbers.
+
+The AST2500 supports a SW generated interrupt
+
+Required properties:
+- reg: address and length of the register for the device.
+- compatible: "aspeed,cvic" and one of:
+               "aspeed,ast2400-cvic"
+             or
+               "aspeed,ast2500-cvic"
+
+- valid-sources: One cell, bitmap of supported sources for the implementation
+
+Optional properties;
+- copro-sw-interrupts: List of interrupt numbers that can be used as
+                      SW interrupts from the ARM to the coprocessor.
+                      (AST2500 only)
+
+Example:
+
+       cvic: copro-interrupt-controller@1e6c2000 {
+               compatible = "aspeed,ast2500-cvic";
+               valid-sources = <0xffffffff>;
+               copro-sw-interrupts = <1>;
+               reg = <0x1e6c2000 0x80>;
+       };
--

2.17.1

On Mon, Jun 18, 2018 at 02:59:00PM +1000, Benjamin Herrenschmidt wrote:

aspeed,valid-sources

This could use a better description. I thought this was which bits to 
use for s/w irq, but then I read the next property...

Alternatively, why can't this be implied by the compatible?

+
+Optional properties;
+- copro-sw-interrupts: List of interrupt numbers that can be used as
+		       SW interrupts from the ARM to the coprocessor.
+		       (AST2500 only)
+
+Example:
+
+	cvic: copro-interrupt-controller@1e6c2000 {
+		compatible = "aspeed,ast2500-cvic";
+		valid-sources = <0xffffffff>;
+		copro-sw-interrupts = <1>;
+		reg = <0x1e6c2000 0x80>;
+	};
-- 
2.17.1


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On Wed, 2018-06-20 at 13:49 -0600, Rob Herring wrote:

On Mon, Jun 18, 2018 at 02:59:00PM +1000, Benjamin Herrenschmidt wrote:

quoted

Add the device-tree binding definition for the AST2400
and AST2500 coprocessor interrupt controller

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
 .../devicetree/bindings/misc/aspeed,cvic.txt  | 35 +++++++++++++++++++
 1 file changed, 35 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/misc/aspeed,cvic.txt

diff --git a/Documentation/devicetree/bindings/misc/aspeed,cvic.txt b/Documentation/devicetree/bindings/misc/aspeed,cvic.txt
new file mode 100644
index 000000000000..2562e2991e4d
--- /dev/null
+++ b/Documentation/devicetree/bindings/misc/aspeed,cvic.txt

@@ -0,0 +1,35 @@
+* Aspeed AST2400 and AST2500 coprocessor interrupt controller
+
+This file describes the bindings for the interrupt controller present
+in the AST2400 and AST2500 BMC SoCs which provides interrupt to the
+ColdFire coprocessor.
+
+It is not a normal interrupt controller and it would be rather
+inconvenient to create an interrupt tree for it as it somewhat shares
+some of the same sources as the main ARM interrupt controller but with
+different numbers.
+
+The AST2500 supports a SW generated interrupt
+
+Required properties:
+- reg: address and length of the register for the device.
+- compatible: "aspeed,cvic" and one of:
+		"aspeed,ast2400-cvic"
+	      or
+		"aspeed,ast2500-cvic"
+
+- valid-sources: One cell, bitmap of supported sources for the implementation

aspeed,valid-sources

This could use a better description. I thought this was which bits to 
use for s/w irq, but then I read the next property...

Alternatively, why can't this be implied by the compatible?

It could, I'm happy to drop it, I don't actually use it in SW.

Cheers,
Ben.

quoted

+
+Optional properties;
+- copro-sw-interrupts: List of interrupt numbers that can be used as
+		       SW interrupts from the ARM to the coprocessor.
+		       (AST2500 only)
+
+Example:
+
+	cvic: copro-interrupt-controller@1e6c2000 {
+		compatible = "aspeed,ast2500-cvic";
+		valid-sources = <0xffffffff>;
+		copro-sw-interrupts = <1>;
+		reg = <0x1e6c2000 0x80>;
+	};
-- 
2.17.1


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