These are basic device tree files needed to boot a SDM845 MTP
board to a ramfs based serial console shell
Bindings are based on whats proposed for pinctrl/serial/clock
drivers for SDM845 SoC
pinctrl: https://patchwork.kernel.org/patch/10157143/ (This is now pulled
in by Linus Walleij for 4.17)
clocks: https://lkml.org/lkml/2018/1/31/209 (under review)
serial: https://patchwork.ozlabs.org/cover/860251/ (under review)
'PATCH 3/3' is based on v2 of serial patches, will need an update if
v3 (still in the works) has further binding updates
Since 'PATCH 2/3' also adds an ITS node and keeps it disabled, we also depend
on https://lkml.org/lkml/2018/1/29/383
changes in v4:
* pull config changes to uart pins
* License in device tree files is still GPL-2.0
changes in v3:
* split the pinmux/pinconf nodes across SoC/Board files
* Fixes for issues reported with 'make dtbs W=2'
* other minor fixes based on review
changes in v2:
* dropped cpu-map
* dropped GIC_CPU_MASK_SIMPLE()
* Added new cpu compatible for kryo385
* added ITS node, marked as disabled
Rajendra Nayak (4):
dt-bindings: arm: Document kryo385 cpu
dt-bindings: qcom: Add SDM845 bindings
arm64: dts: sdm845: Add minimal dts/dtsi files for sdm845 SoC and MTP
arm64: dts: sdm845: Add serial console support
Documentation/devicetree/bindings/arm/cpus.txt | 1 +
Documentation/devicetree/bindings/arm/qcom.txt | 1 +
arch/arm64/boot/dts/qcom/Makefile | 1 +
arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 54 +++++
arch/arm64/boot/dts/qcom/sdm845.dtsi | 316 +++++++++++++++++++++++++
5 files changed, 373 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/sdm845-mtp.dts
create mode 100644 arch/arm64/boot/dts/qcom/sdm845.dtsi
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
Document the compatible string for the Kryo385 cpus found in qualcomm
SoCs.
Signed-off-by: Rajendra Nayak <redacted>
Reviewed-by: Rob Herring <robh@kernel.org>
---
Documentation/devicetree/bindings/arm/cpus.txt | 1 +
1 file changed, 1 insertion(+)
@@ -26,6 +26,7 @@ The 'SoC' element must be one of the following strings: msm8996 mdm9615 ipq8074+ sdm845 The 'board' element must be one of the following strings:
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
@@ -0,0 +1,277 @@+// SPDX-License-Identifier: GPL-2.0+/*+*SDM845SoCdevicetreesource+*+*Copyright(c)2018,TheLinuxFoundation.Allrightsreserved.+*/++#include<dt-bindings/interrupt-controller/arm-gic.h>++/{+interrupt-parent=<&intc>;++#address-cells=<2>;+#size-cells=<2>;++chosen{};++memory@80000000{+device_type="memory";+/* We expect the bootloader to fill in the size */+reg=<00x8000000000>;+};++cpus{+#address-cells=<2>;+#size-cells=<0>;++CPU0:cpu@0{+device_type="cpu";+compatible="qcom,kryo385";+reg=<0x00x0>;+enable-method="psci";+next-level-cache=<&L2_0>;+L2_0:l2-cache{+compatible="cache";+next-level-cache=<&L3_0>;+L3_0:l3-cache{+compatible="cache";+};+};+};++CPU1:cpu@100{+device_type="cpu";+compatible="qcom,kryo385";+reg=<0x00x100>;+enable-method="psci";+next-level-cache=<&L2_100>;+L2_100:l2-cache{+compatible="cache";+next-level-cache=<&L3_0>;+};+};++CPU2:cpu@200{+device_type="cpu";+compatible="qcom,kryo385";+reg=<0x00x200>;+enable-method="psci";+next-level-cache=<&L2_200>;+L2_200:l2-cache{+compatible="cache";+next-level-cache=<&L3_0>;+};+};++CPU3:cpu@300{+device_type="cpu";+compatible="qcom,kryo385";+reg=<0x00x300>;+enable-method="psci";+next-level-cache=<&L2_300>;+L2_300:l2-cache{+compatible="cache";+next-level-cache=<&L3_0>;+};+};++CPU4:cpu@400{+device_type="cpu";+compatible="qcom,kryo385";+reg=<0x00x400>;+enable-method="psci";+next-level-cache=<&L2_400>;+L2_400:l2-cache{+compatible="cache";+next-level-cache=<&L3_0>;+};+};++CPU5:cpu@500{+device_type="cpu";+compatible="qcom,kryo385";+reg=<0x00x500>;+enable-method="psci";+next-level-cache=<&L2_500>;+L2_500:l2-cache{+compatible="cache";+next-level-cache=<&L3_0>;+};+};++CPU6:cpu@600{+device_type="cpu";+compatible="qcom,kryo385";+reg=<0x00x600>;+enable-method="psci";+next-level-cache=<&L2_600>;+L2_600:l2-cache{+compatible="cache";+next-level-cache=<&L3_0>;+};+};++CPU7:cpu@700{+device_type="cpu";+compatible="qcom,kryo385";+reg=<0x00x700>;+enable-method="psci";+next-level-cache=<&L2_700>;+L2_700:l2-cache{+compatible="cache";+next-level-cache=<&L3_0>;+};+};+};++timer{+compatible="arm,armv8-timer";+interrupts=<GIC_PPI1IRQ_TYPE_LEVEL_LOW>,+<GIC_PPI2IRQ_TYPE_LEVEL_LOW>,+<GIC_PPI3IRQ_TYPE_LEVEL_LOW>,+<GIC_PPI0IRQ_TYPE_LEVEL_LOW>;+};++clocks{+xo_board:xo-board{+compatible="fixed-clock";+#clock-cells=<0>;+clock-frequency=<19200000>;+};++sleep_clk:sleep-clk{+compatible="fixed-clock";+#clock-cells=<0>;+clock-frequency=<32764>;+};+};++psci{+compatible="arm,psci-1.0";+method="smc";+};++soc:soc{+#address-cells=<1>;+#size-cells=<1>;+ranges=<0000xffffffff>;+compatible="simple-bus";++intc:interrupt-controller@17a00000{+compatible="arm,gic-v3";+#address-cells=<1>;+#size-cells=<1>;+ranges;+#interrupt-cells=<3>;+interrupt-controller;+#redistributor-regions=<1>;+redistributor-stride=<0x00x20000>;+reg=<0x17a000000x10000>,/* GICD */+<0x17a600000x100000>;/* GICR * 8 */+interrupts=<GIC_PPI9IRQ_TYPE_LEVEL_HIGH>;++gic-its@17a40000{+compatible="arm,gic-v3-its";+msi-controller;+#msi-cells=<1>;+reg=<0x17a400000x20000>;+status="disabled";+};+};++gcc:clock-controller@100000{+compatible="qcom,gcc-sdm845";+reg=<0x1000000x1f0000>;+#clock-cells=<1>;+#reset-cells=<1>;+};++tlmm:pinctrl@3400000{+compatible="qcom,sdm845-pinctrl";+reg=<0x034000000xc00000>;+interrupts=<GIC_SPI208IRQ_TYPE_NONE>;+gpio-controller;+#gpio-cells=<2>;+interrupt-controller;+#interrupt-cells=<2>;+};++timer@17c90000{+#address-cells=<1>;+#size-cells=<1>;+ranges;+compatible="arm,armv7-timer-mem";+reg=<0x17c900000x1000>;++frame@17ca0000{+frame-number=<0>;+interrupts=<GIC_SPI7IRQ_TYPE_LEVEL_HIGH>,+<GIC_SPI6IRQ_TYPE_LEVEL_HIGH>;+reg=<0x17ca00000x1000>,+<0x17cb00000x1000>;+};++frame@17cc0000{+frame-number=<1>;+interrupts=<GIC_SPI8IRQ_TYPE_LEVEL_HIGH>;+reg=<0x17cc00000x1000>;+status="disabled";+};++frame@17cd0000{+frame-number=<2>;+interrupts=<GIC_SPI9IRQ_TYPE_LEVEL_HIGH>;+reg=<0x17cd00000x1000>;+status="disabled";+};++frame@17ce0000{+frame-number=<3>;+interrupts=<GIC_SPI10IRQ_TYPE_LEVEL_HIGH>;+reg=<0x17ce00000x1000>;+status="disabled";+};++frame@17cf0000{+frame-number=<4>;+interrupts=<GIC_SPI11IRQ_TYPE_LEVEL_HIGH>;+reg=<0x17cf00000x1000>;+status="disabled";+};++frame@17d00000{+frame-number=<5>;+interrupts=<GIC_SPI12IRQ_TYPE_LEVEL_HIGH>;+reg=<0x17d000000x1000>;+status="disabled";+};++frame@17d10000{+frame-number=<6>;+interrupts=<GIC_SPI13IRQ_TYPE_LEVEL_HIGH>;+reg=<0x17d100000x1000>;+status="disabled";+};+};++spmi_bus:spmi@c440000{+compatible="qcom,spmi-pmic-arb";+reg=<0xc4400000x1100>,+<0xc6000000x2000000>,+<0xe6000000x100000>,+<0xe7000000xa0000>,+<0xc40a0000x26000>;+reg-names="core","chnls","obsrvr","intr","cnfg";+interrupt-names="periph_irq";+interrupts=<GIC_SPI481IRQ_TYPE_NONE>;+qcom,ee=<0>;+qcom,channel=<0>;+#address-cells=<2>;+#size-cells=<0>;+interrupt-controller;+#interrupt-cells=<4>;+cell-index=<0>;+};+};+};
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
Add the qup uart node and geni se instance needed to
support the serial console on the MTP.
Signed-off-by: Rajendra Nayak <redacted>
---
arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 39 +++++++++++++++++++++++++++++++++
arch/arm64/boot/dts/qcom/sdm845.dtsi | 39 +++++++++++++++++++++++++++++++++
2 files changed, 78 insertions(+)
From: Doug Anderson <dianders@chromium.org> Date: 2018-02-16 19:27:41
Hi,
On Thu, Feb 15, 2018 at 10:05 PM, Rajendra Nayak [off-list ref] wrote:
Document the compatible string for the Kryo385 cpus found in qualcomm
SoCs.
Signed-off-by: Rajendra Nayak <redacted>
Reviewed-by: Rob Herring <robh@kernel.org>
---
Documentation/devicetree/bindings/arm/cpus.txt | 1 +
1 file changed, 1 insertion(+)
FWIW since my review doesn't add much atop Rob's:
Reviewed-by: Douglas Anderson <dianders@chromium.org>
This already has my Reviewed-by tag (and that's great), but just
making it clear that I am in favor of this landing with just the
GPL-2.0 license and not block waiting on the QC lawyers to hash out
whether the device tree can really be dual-licensed.
If lawyers come back soon then it will be easy to have a followup
patch that changes this. Since (I don't think) any hobbyists have an
SDM845 in their hands right now it seems unlikely to be hard to track
down any authors in the meantime and make sure they're OK.
If lawyers don't come back soon then it will be a good thing that we
didn't block.
Having this skeleton DTS file land sooner rather than later will
unblock other patches to be sent out enabling other peripherals, which
seems like a nice thing. :)
-Doug
From: Doug Anderson <dianders@chromium.org> Date: 2018-02-16 19:28:26
Hi,
On Thu, Feb 15, 2018 at 10:05 PM, Rajendra Nayak [off-list ref] wrote:
Add the qup uart node and geni se instance needed to
support the serial console on the MTP.
Signed-off-by: Rajendra Nayak <redacted>
---
arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 39 +++++++++++++++++++++++++++++++++
arch/arm64/boot/dts/qcom/sdm845.dtsi | 39 +++++++++++++++++++++++++++++++++
2 files changed, 78 insertions(+)
Looks nice to me. Thanks!
As in your cover letter, this patch will almost certainly need to be
spun again because it's based on bindings that have review feedback.
For those of you playing along at home, see
<https://patchwork.kernel.org/patch/10162063/>. Thus, I'm not
providing a Reviewed-by tag at the moemnt.
I will still say thanks for posting this (even though it was based on
old bindings) since it allowed us to make some good progress ahead of
time so we'll be very close to landing when the serial patch is spun
next.
In my ideal world the first 3 patches of this series would land sooner
rather than later and then this 4th patch would simply be re-posted on
its own when the bindings get more finalized (or, even better, if the
first 3 patches have landed then Karthikeyan could just glom this on
to the end of his next spin of the serial driver. ;-)
-Doug
@@ -0,0 +1,277 @@+// SPDX-License-Identifier: GPL-2.0+/*+*SDM845SoCdevicetreesource+*+*Copyright(c)2018,TheLinuxFoundation.Allrightsreserved.+*/++#include<dt-bindings/interrupt-controller/arm-gic.h>++/{+interrupt-parent=<&intc>;++#address-cells=<2>;+#size-cells=<2>;++chosen{};++memory@80000000{+device_type="memory";+/* We expect the bootloader to fill in the size */+reg=<00x8000000000>;+};++cpus{+#address-cells=<2>;+#size-cells=<0>;++CPU0:cpu@0{+device_type="cpu";+compatible="qcom,kryo385";+reg=<0x00x0>;+enable-method="psci";+next-level-cache=<&L2_0>;+L2_0:l2-cache{+compatible="cache";+next-level-cache=<&L3_0>;+L3_0:l3-cache{+compatible="cache";+};+};+};++CPU1:cpu@100{+device_type="cpu";+compatible="qcom,kryo385";+reg=<0x00x100>;+enable-method="psci";+next-level-cache=<&L2_100>;+L2_100:l2-cache{+compatible="cache";+next-level-cache=<&L3_0>;+};+};++CPU2:cpu@200{+device_type="cpu";+compatible="qcom,kryo385";+reg=<0x00x200>;+enable-method="psci";+next-level-cache=<&L2_200>;+L2_200:l2-cache{+compatible="cache";+next-level-cache=<&L3_0>;+};+};++CPU3:cpu@300{+device_type="cpu";+compatible="qcom,kryo385";+reg=<0x00x300>;+enable-method="psci";+next-level-cache=<&L2_300>;+L2_300:l2-cache{+compatible="cache";+next-level-cache=<&L3_0>;+};+};++CPU4:cpu@400{+device_type="cpu";+compatible="qcom,kryo385";+reg=<0x00x400>;+enable-method="psci";+next-level-cache=<&L2_400>;+L2_400:l2-cache{+compatible="cache";+next-level-cache=<&L3_0>;+};+};++CPU5:cpu@500{+device_type="cpu";+compatible="qcom,kryo385";+reg=<0x00x500>;+enable-method="psci";+next-level-cache=<&L2_500>;+L2_500:l2-cache{+compatible="cache";+next-level-cache=<&L3_0>;+};+};++CPU6:cpu@600{+device_type="cpu";+compatible="qcom,kryo385";+reg=<0x00x600>;+enable-method="psci";+next-level-cache=<&L2_600>;+L2_600:l2-cache{+compatible="cache";+next-level-cache=<&L3_0>;+};+};++CPU7:cpu@700{+device_type="cpu";+compatible="qcom,kryo385";+reg=<0x00x700>;+enable-method="psci";+next-level-cache=<&L2_700>;+L2_700:l2-cache{+compatible="cache";+next-level-cache=<&L3_0>;+};+};+};++timer{+compatible="arm,armv8-timer";+interrupts=<GIC_PPI1IRQ_TYPE_LEVEL_LOW>,+<GIC_PPI2IRQ_TYPE_LEVEL_LOW>,+<GIC_PPI3IRQ_TYPE_LEVEL_LOW>,+<GIC_PPI0IRQ_TYPE_LEVEL_LOW>;+};++clocks{+xo_board:xo-board{+compatible="fixed-clock";+#clock-cells=<0>;+clock-frequency=<19200000>;+};++sleep_clk:sleep-clk{+compatible="fixed-clock";+#clock-cells=<0>;+clock-frequency=<32764>;+};+};++psci{+compatible="arm,psci-1.0";+method="smc";+};++soc:soc{+#address-cells=<1>;+#size-cells=<1>;+ranges=<0000xffffffff>;+compatible="simple-bus";++intc:interrupt-controller@17a00000{+compatible="arm,gic-v3";+#address-cells=<1>;+#size-cells=<1>;+ranges;+#interrupt-cells=<3>;+interrupt-controller;+#redistributor-regions=<1>;+redistributor-stride=<0x00x20000>;+reg=<0x17a000000x10000>,/* GICD */+<0x17a600000x100000>;/* GICR * 8 */+interrupts=<GIC_PPI9IRQ_TYPE_LEVEL_HIGH>;++gic-its@17a40000{+compatible="arm,gic-v3-its";+msi-controller;+#msi-cells=<1>;+reg=<0x17a400000x20000>;+status="disabled";+};+};++gcc:clock-controller@100000{+compatible="qcom,gcc-sdm845";+reg=<0x1000000x1f0000>;+#clock-cells=<1>;+#reset-cells=<1>;+};++tlmm:pinctrl@3400000{+compatible="qcom,sdm845-pinctrl";+reg=<0x034000000xc00000>;+interrupts=<GIC_SPI208IRQ_TYPE_NONE>;
Please do not use IRQ_TYPE_NONE, ever. It doesn't exist in the GIC
binding. Set it to the actual trigger value.
@@ -26,6 +26,7 @@ The 'SoC' element must be one of the following strings: msm8996 mdm9615 ipq8074+ sdm845
These should really be the full string with 'qcom,', but you don't have
to fix that now.
Reviewed-by: Rob Herring <robh@kernel.org>
Thanks for the review! I agree that we should land this and then make
further progress in additional patches.
Are you suggesting to rewriting this whole bindings doc to not specify
things in an "M x N" type of way? AKA the top of this doc says:
Each board must specify a top-level board compatible string with the following
format:
compatible = "qcom,<SoC>[-<soc_version>][-<foundry_id>]-<board>[/<subtype>][-<board_version>]"
The 'SoC' and 'board' elements are required. All other elements are optional.
...and then the doc goes on to give lists of known SoC and board values.
Presumably if someone were to fix this then they'd need to try to
track down existing boards so they could enumerate every known
combination?
-Doug
From: Doug Anderson <dianders@chromium.org> Date: 2018-02-21 23:24:02
Hi,
On Mon, Feb 19, 2018 at 8:36 AM, Marc Zyngier [off-list ref] wrote:
quoted
+ interrupts = <GIC_SPI 208 IRQ_TYPE_NONE>;
Please do not use IRQ_TYPE_NONE, ever. It doesn't exist in the GIC
binding. Set it to the actual trigger value.
quoted
+ interrupts = <GIC_SPI 481 IRQ_TYPE_NONE>;
Same here.
Thanks for the review Marc!
Andy: If I'm reading everything correctly you're the one who would
collect these patches and apply them. Is that right? Do they look OK
to you in general? Would you prefer that Rajendra send out a v5 with
the fixes pointed out by Marc, or would you prefer to fix them up
yourself when applying? Is now a good time or would you prefer to
wait?
Thanks! :)
-Doug
@@ -26,6 +26,7 @@ The 'SoC' element must be one of the following strings: msm8996 mdm9615 ipq8074+ sdm845
These should really be the full string with 'qcom,', but you don't have
to fix that now.
Reviewed-by: Rob Herring <robh@kernel.org>
Thanks for the review! I agree that we should land this and then make
further progress in additional patches.
Are you suggesting to rewriting this whole bindings doc to not specify
things in an "M x N" type of way? AKA the top of this doc says:
quoted
Each board must specify a top-level board compatible string with the following
format:
compatible = "qcom,<SoC>[-<soc_version>][-<foundry_id>]-<board>[/<subtype>][-<board_version>]"
The 'SoC' and 'board' elements are required. All other elements are optional.
...and then the doc goes on to give lists of known SoC and board values.
Presumably if someone were to fix this then they'd need to try to
track down existing boards so they could enumerate every known
combination?
Ah, I forgot about all this QCom craziness. NM.
Though I'm not sure any of these optional suffixes ever got
implemented. AFAIK, downstream still uses those separate board-id
properties (though the bootloaders can finally deal with them being
absent).
Rob
Please do not use IRQ_TYPE_NONE, ever. It doesn't exist in the GIC
binding. Set it to the actual trigger value.
Thanks Marc for the review. I fixed these up and did a respin.
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by The Linux Foundation
Hi,
On Mon, Feb 19, 2018 at 8:36 AM, Marc Zyngier [off-list ref] wrote:
quoted
quoted
+ interrupts = <GIC_SPI 208 IRQ_TYPE_NONE>;
Please do not use IRQ_TYPE_NONE, ever. It doesn't exist in the GIC
binding. Set it to the actual trigger value.
quoted
quoted
+ interrupts = <GIC_SPI 481 IRQ_TYPE_NONE>;
Same here.
Thanks for the review Marc!
Andy: If I'm reading everything correctly you're the one who would
collect these patches and apply them. Is that right? Do they look OK
to you in general? Would you prefer that Rajendra send out a v5 with
the fixes pointed out by Marc, or would you prefer to fix them up
yourself when applying? Is now a good time or would you prefer to
wait?
I just fixed up to remove all instances of IRQ_TYPE_NONE and sent a v5 out.