2017年1月6日 06:08于 Maxime Ripard [off-list ref]写道：

On Tue, Dec 27, 2016 at 12:25:13AM +0800, Icenowy Zheng wrote: 

quoted

Based on the Allwinner H5 datasheet and the pinctrl driver of the 
backward-compatible H3 this introduces the pin multiplex assignments for 
the H5 SoC. 

H5 introduced some more pin functions (e.g. three more groups of TS 
pins, and one more groups of SIM pins) than H3. 

Signed-off-by: Icenowy Zheng <redacted> 
--- 
 .../bindings/pinctrl/allwinner,sunxi-pinctrl.txt   |   1 + 
 drivers/pinctrl/sunxi/Kconfig                      |   4 + 
 drivers/pinctrl/sunxi/Makefile                     |   1 + 
 drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c          | 551 +++++++++++++++++++++ 
 4 files changed, 557 insertions(+) 
 create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c 

diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt 
index c931fb1c01a6..2fd688c8dbdb 100644 
--- a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt 
+++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt 

@@ -23,6 +23,7 @@ Required properties: 

   "allwinner,sun8i-h3-pinctrl" 
   "allwinner,sun8i-h3-r-pinctrl" 
   "allwinner,sun50i-a64-pinctrl" 
+  "allwinner,sun50i-h5-r-pinctrl" 

You're using a different compatible in your driver. 

oh... just drop "-r".

R_PIO in H5 is the same with H3.

quoted

   "nextthing,gr8-pinctrl" 
 
 - reg: Should contain the register physical address and length for the 

diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig 
index bff1ffc6f01e..e9c47e8b2ee0 100644 
--- a/drivers/pinctrl/sunxi/Kconfig 
+++ b/drivers/pinctrl/sunxi/Kconfig 

@@ -76,4 +76,8 @@ config PINCTRL_SUN50I_A64 
 bool 
 select PINCTRL_SUNXI 
 
+config PINCTRL_SUN50I_H5 
+ bool 
+ select PINCTRL_SUNXI 
+ 
 endif 

diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile 
index 95f93d0561fc..bab215d25440 100644 
--- a/drivers/pinctrl/sunxi/Makefile 
+++ b/drivers/pinctrl/sunxi/Makefile 

@@ -17,5 +17,6 @@ obj-$(CONFIG_PINCTRL_SUN50I_A64) += pinctrl-sun50i-a64.o 
 obj-$(CONFIG_PINCTRL_SUN8I_A83T) += pinctrl-sun8i-a83t.o 
 obj-$(CONFIG_PINCTRL_SUN8I_H3) += pinctrl-sun8i-h3.o 
 obj-$(CONFIG_PINCTRL_SUN8I_H3_R) += pinctrl-sun8i-h3-r.o 
+obj-$(CONFIG_PINCTRL_SUN50I_H5) += pinctrl-sun50i-h5.o 
 obj-$(CONFIG_PINCTRL_SUN9I_A80) += pinctrl-sun9i-a80.o 
 obj-$(CONFIG_PINCTRL_SUN9I_A80_R) += pinctrl-sun9i-a80-r.o 

diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c 
new file mode 100644 
index 000000000000..67a55df37782 
--- /dev/null 
+++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c 

@@ -0,0 +1,551 @@ 
+/* 
+ * Allwinner H5 SoC pinctrl driver. 
+ * 
+ * Copyright (C) 2016 Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org> 
+ * 
+ * Based on pinctrl-sun8i-h3.c, which is: 
+ * Copyright (C) 2015 Jens Kuske <jenskuske-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> 
+ * 
+ * Based on pinctrl-sun8i-a23.c, which is: 
+ * Copyright (C) 2014 Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org> 
+ * Copyright (C) 2014 Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org> 
+ * 
+ * This file is licensed under the terms of the GNU General Public 
+ * License version 2.  This program is licensed "as is" without any 
+ * warranty of any kind, whether express or implied. 
+ */ 
+ 
+#include <linux/module.h> 
+#include <linux/platform_device.h> 
+#include <linux/of.h> 
+#include <linux/of_device.h> 
+#include <linux/pinctrl/pinctrl.h> 
+ 
+#include "pinctrl-sunxi.h" 
+ 
+static const struct sunxi_desc_pin sun50i_h5_pins[] = { 
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0), 
+   SUNXI_FUNCTION(0x0, "gpio_in"), 
+   SUNXI_FUNCTION(0x1, "gpio_out"), 
+   SUNXI_FUNCTION(0x2, "uart2"), /* TX */ 
+   SUNXI_FUNCTION(0x3, "jtag"), /* MS */ 
+   SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PA_EINT0 */ 
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1), 
+   SUNXI_FUNCTION(0x0, "gpio_in"), 
+   SUNXI_FUNCTION(0x1, "gpio_out"), 
+   SUNXI_FUNCTION(0x2, "uart2"), /* RX */ 
+   SUNXI_FUNCTION(0x3, "jtag"), /* CK */ 
+   SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), /* PA_EINT1 */ 
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2), 
+   SUNXI_FUNCTION(0x0, "gpio_in"), 
+   SUNXI_FUNCTION(0x1, "gpio_out"), 
+   SUNXI_FUNCTION(0x2, "uart2"), /* RTS */ 
+   SUNXI_FUNCTION(0x3, "jtag"), /* DO */ 
+   SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), /* PA_EINT2 */ 
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3), 
+   SUNXI_FUNCTION(0x0, "gpio_in"), 
+   SUNXI_FUNCTION(0x1, "gpio_out"), 
+   SUNXI_FUNCTION(0x2, "uart2"), /* CTS */ 
+   SUNXI_FUNCTION(0x3, "jtag"), /* DI */ 
+   SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), /* PA_EINT3 */ 
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4), 
+   SUNXI_FUNCTION(0x0, "gpio_in"), 
+   SUNXI_FUNCTION(0x1, "gpio_out"), 
+   SUNXI_FUNCTION(0x2, "uart0"), /* TX */ 
+   SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), /* PA_EINT4 */ 
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5), 
+   SUNXI_FUNCTION(0x0, "gpio_in"), 
+   SUNXI_FUNCTION(0x1, "gpio_out"), 
+   SUNXI_FUNCTION(0x2, "uart0"), /* RX */ 
+   SUNXI_FUNCTION(0x3, "pwm0"), 
+   SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), /* PA_EINT5 */ 
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6), 
+   SUNXI_FUNCTION(0x0, "gpio_in"), 
+   SUNXI_FUNCTION(0x1, "gpio_out"), 
+   SUNXI_FUNCTION(0x2, "sim"), /* PWREN */ 
+   SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), /* PA_EINT6 */ 
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7), 
+   SUNXI_FUNCTION(0x0, "gpio_in"), 
+   SUNXI_FUNCTION(0x1, "gpio_out"), 
+   SUNXI_FUNCTION(0x2, "sim"), /* CLK */ 
+   SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), /* PA_EINT7 */ 
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 8), 
+   SUNXI_FUNCTION(0x0, "gpio_in"), 
+   SUNXI_FUNCTION(0x1, "gpio_out"), 
+   SUNXI_FUNCTION(0x2, "sim"), /* DATA */ 
+   SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)), /* PA_EINT8 */ 
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 9), 
+   SUNXI_FUNCTION(0x0, "gpio_in"), 
+   SUNXI_FUNCTION(0x1, "gpio_out"), 
+   SUNXI_FUNCTION(0x2, "sim"), /* RST */ 
+   SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), /* PA_EINT9 */ 
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 10), 
+   SUNXI_FUNCTION(0x0, "gpio_in"), 
+   SUNXI_FUNCTION(0x1, "gpio_out"), 
+   SUNXI_FUNCTION(0x2, "sim"), /* DET */ 
+   SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), /* PA_EINT10 */ 
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 11), 
+   SUNXI_FUNCTION(0x0, "gpio_in"), 
+   SUNXI_FUNCTION(0x1, "gpio_out"), 
+   SUNXI_FUNCTION(0x2, "i2c0"), /* SCK */ 
+   SUNXI_FUNCTION(0x3, "di"), /* TX */ 
+   SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)), /* PA_EINT11 */ 
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 12), 
+   SUNXI_FUNCTION(0x0, "gpio_in"), 
+   SUNXI_FUNCTION(0x1, "gpio_out"), 
+   SUNXI_FUNCTION(0x2, "i2c0"), /* SDA */ 
+   SUNXI_FUNCTION(0x3, "di"), /* RX */ 
+   SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 12)), /* PA_EINT12 */ 
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 13), 
+   SUNXI_FUNCTION(0x0, "gpio_in"), 
+   SUNXI_FUNCTION(0x1, "gpio_out"), 
+   SUNXI_FUNCTION(0x2, "spi1"), /* CS */ 
+   SUNXI_FUNCTION(0x3, "uart3"), /* TX */ 
+   SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 13)), /* PA_EINT13 */ 
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 14), 
+   SUNXI_FUNCTION(0x0, "gpio_in"), 
+   SUNXI_FUNCTION(0x1, "gpio_out"), 
+   SUNXI_FUNCTION(0x2, "spi1"), /* CLK */ 
+   SUNXI_FUNCTION(0x3, "uart3"), /* RX */ 
+   SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 14)), /* PA_EINT14 */ 
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 15), 
+   SUNXI_FUNCTION(0x0, "gpio_in"), 
+   SUNXI_FUNCTION(0x1, "gpio_out"), 
+   SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */ 
+   SUNXI_FUNCTION(0x3, "uart3"), /* RTS */ 
+   SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 15)), /* PA_EINT15 */ 
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 16), 
+   SUNXI_FUNCTION(0x0, "gpio_in"), 
+   SUNXI_FUNCTION(0x1, "gpio_out"), 
+   SUNXI_FUNCTION(0x2, "spi1"), /* MISO */ 
+   SUNXI_FUNCTION(0x3, "uart3"), /* CTS */ 
+   SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 16)), /* PA_EINT16 */ 
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 17), 
+   SUNXI_FUNCTION(0x0, "gpio_in"), 
+   SUNXI_FUNCTION(0x1, "gpio_out"), 
+   SUNXI_FUNCTION(0x2, "spdif"), /* OUT */ 
+   SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 17)), /* PA_EINT17 */ 
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 18), 
+   SUNXI_FUNCTION(0x0, "gpio_in"), 
+   SUNXI_FUNCTION(0x1, "gpio_out"), 
+   SUNXI_FUNCTION(0x2, "i2s0"), /* SYNC */ 
+   SUNXI_FUNCTION(0x3, "i2c1"), /* SCK */ 
+   SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 18)), /* PA_EINT18 */ 
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 19), 
+   SUNXI_FUNCTION(0x0, "gpio_in"), 
+   SUNXI_FUNCTION(0x1, "gpio_out"), 
+   SUNXI_FUNCTION(0x2, "i2s0"), /* CLK */ 
+   SUNXI_FUNCTION(0x3, "i2c1"), /* SDA */ 
+   SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 19)), /* PA_EINT19 */ 
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 20), 
+   SUNXI_FUNCTION(0x0, "gpio_in"), 
+   SUNXI_FUNCTION(0x1, "gpio_out"), 
+   SUNXI_FUNCTION(0x2, "i2s0"), /* DOUT */ 
+   SUNXI_FUNCTION(0x3, "sim"), /* VPPEN */ 
+   SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 20)), /* PA_EINT20 */ 
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 21), 
+   SUNXI_FUNCTION(0x0, "gpio_in"), 
+   SUNXI_FUNCTION(0x1, "gpio_out"), 
+   SUNXI_FUNCTION(0x2, "i2s0"), /* DIN */ 
+   SUNXI_FUNCTION(0x3, "sim"), /* VPPPP */ 
+   SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 21)), /* PA_EINT21 */ 
+ /* Hole */ 
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0), 
+   SUNXI_FUNCTION(0x0, "gpio_in"), 
+   SUNXI_FUNCTION(0x1, "gpio_out"), 
+   SUNXI_FUNCTION(0x2, "nand0"), /* WE */ 
+   SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */ 
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1), 
+   SUNXI_FUNCTION(0x0, "gpio_in"), 
+   SUNXI_FUNCTION(0x1, "gpio_out"), 
+   SUNXI_FUNCTION(0x2, "nand0"), /* ALE */ 
+   SUNXI_FUNCTION(0x3, "spi0"), /* MISO */ 
+   SUNXI_FUNCTION(0x4, "mmc2")), /* DS */ 
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2), 
+   SUNXI_FUNCTION(0x0, "gpio_in"), 
+   SUNXI_FUNCTION(0x1, "gpio_out"), 
+   SUNXI_FUNCTION(0x2, "nand0"), /* CLE */ 
+   SUNXI_FUNCTION(0x3, "spi0")), /* CLK */ 
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3), 
+   SUNXI_FUNCTION(0x0, "gpio_in"), 
+   SUNXI_FUNCTION(0x1, "gpio_out"), 
+   SUNXI_FUNCTION(0x2, "nand0"), /* CE1 */ 
+   SUNXI_FUNCTION(0x3, "spi0")), /* CS */ 
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4), 
+   SUNXI_FUNCTION(0x0, "gpio_in"), 
+   SUNXI_FUNCTION(0x1, "gpio_out"), 
+   SUNXI_FUNCTION(0x2, "nand0"), /* CE0 */ 
+   SUNXI_FUNCTION(0x4, "spi0")), /* MISO */ 
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5), 
+   SUNXI_FUNCTION(0x0, "gpio_in"), 
+   SUNXI_FUNCTION(0x1, "gpio_out"), 
+   SUNXI_FUNCTION(0x2, "nand0"), /* RE */ 
+   SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */ 
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6), 
+   SUNXI_FUNCTION(0x0, "gpio_in"), 
+   SUNXI_FUNCTION(0x1, "gpio_out"), 
+   SUNXI_FUNCTION(0x2, "nand0"), /* RB0 */ 
+   SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */ 
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7), 
+   SUNXI_FUNCTION(0x0, "gpio_in"), 
+   SUNXI_FUNCTION(0x1, "gpio_out"), 
+   SUNXI_FUNCTION(0x2, "nand0")), /* RB1 */ 
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8), 
+   SUNXI_FUNCTION(0x0, "gpio_in"), 
+   SUNXI_FUNCTION(0x1, "gpio_out"), 
+   SUNXI_FUNCTION(0x2, "nand0"), /* DQ0 */ 
+   SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */ 
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9), 
+   SUNXI_FUNCTION(0x0, "gpio_in"), 
+   SUNXI_FUNCTION(0x1, "gpio_out"), 
+   SUNXI_FUNCTION(0x2, "nand0"), /* DQ1 */ 
+   SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */ 
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10), 
+   SUNXI_FUNCTION(0x0, "gpio_in"), 
+   SUNXI_FUNCTION(0x1, "gpio_out"), 
+   SUNXI_FUNCTION(0x2, "nand0"), /* DQ2 */ 
+   SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */ 
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11), 
+   SUNXI_FUNCTION(0x0, "gpio_in"), 
+   SUNXI_FUNCTION(0x1, "gpio_out"), 
+   SUNXI_FUNCTION(0x2, "nand0"), /* DQ3 */ 
+   SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */ 
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12), 
+   SUNXI_FUNCTION(0x0, "gpio_in"), 
+   SUNXI_FUNCTION(0x1, "gpio_out"), 
+   SUNXI_FUNCTION(0x2, "nand0"), /* DQ4 */ 
+   SUNXI_FUNCTION(0x3, "mmc2")), /* D4 */ 
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13), 
+   SUNXI_FUNCTION(0x0, "gpio_in"), 
+   SUNXI_FUNCTION(0x1, "gpio_out"), 
+   SUNXI_FUNCTION(0x2, "nand0"), /* DQ5 */ 
+   SUNXI_FUNCTION(0x3, "mmc2")), /* D5 */ 
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14), 
+   SUNXI_FUNCTION(0x0, "gpio_in"), 
+   SUNXI_FUNCTION(0x1, "gpio_out"), 
+   SUNXI_FUNCTION(0x2, "nand0"), /* DQ6 */ 
+   SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */ 
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15), 
+   SUNXI_FUNCTION(0x0, "gpio_in"), 
+   SUNXI_FUNCTION(0x1, "gpio_out"), 
+   SUNXI_FUNCTION(0x2, "nand0"), /* DQ7 */ 
+   SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */ 
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16), 
+   SUNXI_FUNCTION(0x0, "gpio_in"), 
+   SUNXI_FUNCTION(0x1, "gpio_out"), 
+   SUNXI_FUNCTION(0x2, "nand0"), /* DQS */ 
+   SUNXI_FUNCTION(0x3, "mmc2")), /* RST */ 
+ /* Hole */ 
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0), 
+   SUNXI_FUNCTION(0x0, "gpio_in"), 
+   SUNXI_FUNCTION(0x1, "gpio_out"), 
+   SUNXI_FUNCTION(0x2, "emac"), /* RXD3 */ 
+   SUNXI_FUNCTION(0x3, "di"), /* TX */ 
+   SUNXI_FUNCTION(0x4, "ts2")), /* CLK */ 
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1), 
+   SUNXI_FUNCTION(0x0, "gpio_in"), 
+   SUNXI_FUNCTION(0x1, "gpio_out"), 
+   SUNXI_FUNCTION(0x2, "emac"), /* RXD2 */ 
+   SUNXI_FUNCTION(0x3, "di"), /* RX */ 
+   SUNXI_FUNCTION(0x4, "ts2")), /* ERR */ 
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2), 
+   SUNXI_FUNCTION(0x0, "gpio_in"), 
+   SUNXI_FUNCTION(0x1, "gpio_out"), 
+   SUNXI_FUNCTION(0x2, "emac"), /* RXD1 */ 
+   SUNXI_FUNCTION(0x4, "ts2")), /* SYNC */ 
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3), 
+   SUNXI_FUNCTION(0x0, "gpio_in"), 
+   SUNXI_FUNCTION(0x1, "gpio_out"), 
+   SUNXI_FUNCTION(0x2, "emac"), /* RXD0 */ 
+   SUNXI_FUNCTION(0x4, "ts2")), /* DVLD */ 
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4), 
+   SUNXI_FUNCTION(0x0, "gpio_in"), 
+   SUNXI_FUNCTION(0x1, "gpio_out"), 
+   SUNXI_FUNCTION(0x2, "emac"), /* RXCK */ 
+   SUNXI_FUNCTION(0x4, "ts2")), /* D0 */ 
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5), 
+   SUNXI_FUNCTION(0x0, "gpio_in"), 
+   SUNXI_FUNCTION(0x1, "gpio_out"), 
+   SUNXI_FUNCTION(0x2, "emac"), /* RXCTL/RXDV */ 
+   SUNXI_FUNCTION(0x4, "ts2")), /* D1 */ 
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6), 
+   SUNXI_FUNCTION(0x0, "gpio_in"), 
+   SUNXI_FUNCTION(0x1, "gpio_out"), 
+   SUNXI_FUNCTION(0x2, "emac"), /* RXERR */ 
+   SUNXI_FUNCTION(0x4, "ts2")), /* D2 */ 
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7), 
+   SUNXI_FUNCTION(0x0, "gpio_in"), 
+   SUNXI_FUNCTION(0x1, "gpio_out"), 
+   SUNXI_FUNCTION(0x2, "emac"), /* TXD3 */ 
+   SUNXI_FUNCTION(0x4, "ts2"), /* D3 */ 
+   SUNXI_FUNCTION(0x5, "ts3")), /* CLK */ 
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8), 
+   SUNXI_FUNCTION(0x0, "gpio_in"), 
+   SUNXI_FUNCTION(0x1, "gpio_out"), 
+   SUNXI_FUNCTION(0x2, "emac"), /* TXD2 */ 
+   SUNXI_FUNCTION(0x4, "ts2"), /* D4 */ 
+   SUNXI_FUNCTION(0x5, "ts3")), /* ERR */ 
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9), 
+   SUNXI_FUNCTION(0x0, "gpio_in"), 
+   SUNXI_FUNCTION(0x1, "gpio_out"), 
+   SUNXI_FUNCTION(0x2, "emac"), /* TXD1 */ 
+   SUNXI_FUNCTION(0x4, "ts2"), /* D5 */ 
+   SUNXI_FUNCTION(0x5, "ts3")), /* SYNC */ 
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10), 
+   SUNXI_FUNCTION(0x0, "gpio_in"), 
+   SUNXI_FUNCTION(0x1, "gpio_out"), 
+   SUNXI_FUNCTION(0x2, "emac"), /* TXD0 */ 
+   SUNXI_FUNCTION(0x4, "ts2"), /* D6 */ 
+   SUNXI_FUNCTION(0x5, "ts3")), /* DVLD */ 
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11), 
+   SUNXI_FUNCTION(0x0, "gpio_in"), 
+   SUNXI_FUNCTION(0x1, "gpio_out"), 
+   SUNXI_FUNCTION(0x2, "emac"), /* CRS */ 
+   SUNXI_FUNCTION(0x4, "ts2"), /* D7 */ 
+   SUNXI_FUNCTION(0x5, "ts3")), /* D0 */ 
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12), 
+   SUNXI_FUNCTION(0x0, "gpio_in"), 
+   SUNXI_FUNCTION(0x1, "gpio_out"), 
+   SUNXI_FUNCTION(0x2, "emac"), /* TXCK */ 
+   SUNXI_FUNCTION(0x4, "sim")), /* PWREN */ 
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13), 
+   SUNXI_FUNCTION(0x0, "gpio_in"), 
+   SUNXI_FUNCTION(0x1, "gpio_out"), 
+   SUNXI_FUNCTION(0x2, "emac"), /* TXCTL/TXEN */ 
+   SUNXI_FUNCTION(0x4, "sim")), /* CLK */ 
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14), 
+   SUNXI_FUNCTION(0x0, "gpio_in"), 
+   SUNXI_FUNCTION(0x1, "gpio_out"), 
+   SUNXI_FUNCTION(0x2, "emac"), /* TXERR */ 
+   SUNXI_FUNCTION(0x4, "sim")), /* DATA */ 
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15), 
+   SUNXI_FUNCTION(0x0, "gpio_in"), 
+   SUNXI_FUNCTION(0x1, "gpio_out"), 
+   SUNXI_FUNCTION(0x2, "emac"), /* CLKIN/COL */ 
+   SUNXI_FUNCTION(0x4, "sim")), /* RST */ 
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16), 
+   SUNXI_FUNCTION(0x0, "gpio_in"), 
+   SUNXI_FUNCTION(0x1, "gpio_out"), 
+   SUNXI_FUNCTION(0x2, "emac"), /* MDC */ 
+   SUNXI_FUNCTION(0x4, "sim")), /* DET */ 
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17), 
+   SUNXI_FUNCTION(0x0, "gpio_in"), 
+   SUNXI_FUNCTION(0x1, "gpio_out"), 
+   SUNXI_FUNCTION(0x2, "emac")), /* MDIO */ 
+ /* Hole */ 
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0), 
+   SUNXI_FUNCTION(0x0, "gpio_in"), 
+   SUNXI_FUNCTION(0x1, "gpio_out"), 
+   SUNXI_FUNCTION(0x2, "csi"), /* PCLK */ 
+   SUNXI_FUNCTION(0x3, "ts0")), /* CLK */ 
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1), 
+   SUNXI_FUNCTION(0x0, "gpio_in"), 
+   SUNXI_FUNCTION(0x1, "gpio_out"), 
+   SUNXI_FUNCTION(0x2, "csi"), /* MCLK */ 
+   SUNXI_FUNCTION(0x3, "ts0")), /* ERR */ 
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2), 
+   SUNXI_FUNCTION(0x0, "gpio_in"), 
+   SUNXI_FUNCTION(0x1, "gpio_out"), 
+   SUNXI_FUNCTION(0x2, "csi"), /* HSYNC */ 
+   SUNXI_FUNCTION(0x3, "ts0")), /* SYNC */ 
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3), 
+   SUNXI_FUNCTION(0x0, "gpio_in"), 
+   SUNXI_FUNCTION(0x1, "gpio_out"), 
+   SUNXI_FUNCTION(0x2, "csi"), /* VSYNC */ 
+   SUNXI_FUNCTION(0x3, "ts0")), /* DVLD */ 
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4), 
+   SUNXI_FUNCTION(0x0, "gpio_in"), 
+   SUNXI_FUNCTION(0x1, "gpio_out"), 
+   SUNXI_FUNCTION(0x2, "csi"), /* D0 */ 
+   SUNXI_FUNCTION(0x3, "ts0")), /* D0 */ 
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5), 
+   SUNXI_FUNCTION(0x0, "gpio_in"), 
+   SUNXI_FUNCTION(0x1, "gpio_out"), 
+   SUNXI_FUNCTION(0x2, "csi"), /* D1 */ 
+   SUNXI_FUNCTION(0x3, "ts0")), /* D1 */ 
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6), 
+   SUNXI_FUNCTION(0x0, "gpio_in"), 
+   SUNXI_FUNCTION(0x1, "gpio_out"), 
+   SUNXI_FUNCTION(0x2, "csi"), /* D2 */ 
+   SUNXI_FUNCTION(0x3, "ts0")), /* D2 */ 
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7), 
+   SUNXI_FUNCTION(0x0, "gpio_in"), 
+   SUNXI_FUNCTION(0x1, "gpio_out"), 
+   SUNXI_FUNCTION(0x2, "csi"), /* D3 */ 
+   SUNXI_FUNCTION(0x3, "ts0"), /* D3 */ 
+   SUNXI_FUNCTION(0x4, "ts1")), /* CLK */ 
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8), 
+   SUNXI_FUNCTION(0x0, "gpio_in"), 
+   SUNXI_FUNCTION(0x1, "gpio_out"), 
+   SUNXI_FUNCTION(0x2, "csi"), /* D4 */ 
+   SUNXI_FUNCTION(0x3, "ts0"), /* D4 */ 
+   SUNXI_FUNCTION(0x4, "ts1")), /* ERR */ 
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9), 
+   SUNXI_FUNCTION(0x0, "gpio_in"), 
+   SUNXI_FUNCTION(0x1, "gpio_out"), 
+   SUNXI_FUNCTION(0x2, "csi"), /* D5 */ 
+   SUNXI_FUNCTION(0x3, "ts0"), /* D5 */ 
+   SUNXI_FUNCTION(0x4, "ts1")), /* SYNC */ 
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10), 
+   SUNXI_FUNCTION(0x0, "gpio_in"), 
+   SUNXI_FUNCTION(0x1, "gpio_out"), 
+   SUNXI_FUNCTION(0x2, "csi"), /* D6 */ 
+   SUNXI_FUNCTION(0x3, "ts0"), /* D6 */ 
+   SUNXI_FUNCTION(0x4, "ts1")), /* DVLD */ 
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11), 
+   SUNXI_FUNCTION(0x0, "gpio_in"), 
+   SUNXI_FUNCTION(0x1, "gpio_out"), 
+   SUNXI_FUNCTION(0x2, "csi"), /* D7 */ 
+   SUNXI_FUNCTION(0x3, "ts"), /* D7 */ 
+   SUNXI_FUNCTION(0x4, "ts1")), /* D0 */ 
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12), 
+   SUNXI_FUNCTION(0x0, "gpio_in"), 
+   SUNXI_FUNCTION(0x1, "gpio_out"), 
+   SUNXI_FUNCTION(0x2, "csi"), /* SCK */ 
+   SUNXI_FUNCTION(0x3, "i2c2")), /* SCK */ 
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13), 
+   SUNXI_FUNCTION(0x0, "gpio_in"), 
+   SUNXI_FUNCTION(0x1, "gpio_out"), 
+   SUNXI_FUNCTION(0x2, "csi"), /* SDA */ 
+   SUNXI_FUNCTION(0x3, "i2c2")), /* SDA */ 
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14), 
+   SUNXI_FUNCTION(0x0, "gpio_in"), 
+   SUNXI_FUNCTION(0x1, "gpio_out"), 
+   SUNXI_FUNCTION(0x3, "sim")), /* VPPEN */ 
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 15), 
+   SUNXI_FUNCTION(0x0, "gpio_in"), 
+   SUNXI_FUNCTION(0x1, "gpio_out"), 
+   SUNXI_FUNCTION(0x3, "sim")), /* VPPPP */ 
+ /* Hole */ 
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0), 
+   SUNXI_FUNCTION(0x0, "gpio_in"), 
+   SUNXI_FUNCTION(0x1, "gpio_out"), 
+   SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */ 
+   SUNXI_FUNCTION(0x3, "jtag")), /* MS */ 
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1), 
+   SUNXI_FUNCTION(0x0, "gpio_in"), 
+   SUNXI_FUNCTION(0x1, "gpio_out"), 
+   SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */ 
+   SUNXI_FUNCTION(0x3, "jtag")), /* DI */ 
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2), 
+   SUNXI_FUNCTION(0x0, "gpio_in"), 
+   SUNXI_FUNCTION(0x1, "gpio_out"), 
+   SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */ 
+   SUNXI_FUNCTION(0x3, "uart0")), /* TX */ 
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3), 
+   SUNXI_FUNCTION(0x0, "gpio_in"), 
+   SUNXI_FUNCTION(0x1, "gpio_out"), 
+   SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */ 
+   SUNXI_FUNCTION(0x3, "jtag")), /* DO */ 
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4), 
+   SUNXI_FUNCTION(0x0, "gpio_in"), 
+   SUNXI_FUNCTION(0x1, "gpio_out"), 
+   SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */ 
+   SUNXI_FUNCTION(0x3, "uart0")), /* RX */ 
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5), 
+   SUNXI_FUNCTION(0x0, "gpio_in"), 
+   SUNXI_FUNCTION(0x1, "gpio_out"), 
+   SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */ 
+   SUNXI_FUNCTION(0x3, "jtag")), /* CK */ 
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 6), 
+   SUNXI_FUNCTION(0x0, "gpio_in"), 
+   SUNXI_FUNCTION(0x1, "gpio_out")), 
+ /* Hole */ 
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0), 
+   SUNXI_FUNCTION(0x0, "gpio_in"), 
+   SUNXI_FUNCTION(0x1, "gpio_out"), 
+   SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */ 
+   SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)), /* PG_EINT0 */ 
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1), 
+   SUNXI_FUNCTION(0x0, "gpio_in"), 
+   SUNXI_FUNCTION(0x1, "gpio_out"), 
+   SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */ 
+   SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)), /* PG_EINT1 */ 
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2), 
+   SUNXI_FUNCTION(0x0, "gpio_in"), 
+   SUNXI_FUNCTION(0x1, "gpio_out"), 
+   SUNXI_FUNCTION(0x2, "mmc1"), /* D0 */ 
+   SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)), /* PG_EINT2 */ 
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3), 
+   SUNXI_FUNCTION(0x0, "gpio_in"), 
+   SUNXI_FUNCTION(0x1, "gpio_out"), 
+   SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */ 
+   SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)), /* PG_EINT3 */ 
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4), 
+   SUNXI_FUNCTION(0x0, "gpio_in"), 
+   SUNXI_FUNCTION(0x1, "gpio_out"), 
+   SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */ 
+   SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)), /* PG_EINT4 */ 
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5), 
+   SUNXI_FUNCTION(0x0, "gpio_in"), 
+   SUNXI_FUNCTION(0x1, "gpio_out"), 
+   SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */ 
+   SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)), /* PG_EINT5 */ 
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6), 
+   SUNXI_FUNCTION(0x0, "gpio_in"), 
+   SUNXI_FUNCTION(0x1, "gpio_out"), 
+   SUNXI_FUNCTION(0x2, "uart1"), /* TX */ 
+   SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)), /* PG_EINT6 */ 
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7), 
+   SUNXI_FUNCTION(0x0, "gpio_in"), 
+   SUNXI_FUNCTION(0x1, "gpio_out"), 
+   SUNXI_FUNCTION(0x2, "uart1"), /* RX */ 
+   SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 7)), /* PG_EINT7 */ 
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8), 
+   SUNXI_FUNCTION(0x0, "gpio_in"), 
+   SUNXI_FUNCTION(0x1, "gpio_out"), 
+   SUNXI_FUNCTION(0x2, "uart1"), /* RTS */ 
+   SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 8)), /* PG_EINT8 */ 
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9), 
+   SUNXI_FUNCTION(0x0, "gpio_in"), 
+   SUNXI_FUNCTION(0x1, "gpio_out"), 
+   SUNXI_FUNCTION(0x2, "uart1"), /* CTS */ 
+   SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 9)), /* PG_EINT9 */ 
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10), 
+   SUNXI_FUNCTION(0x0, "gpio_in"), 
+   SUNXI_FUNCTION(0x1, "gpio_out"), 
+   SUNXI_FUNCTION(0x2, "i2s1"), /* SYNC */ 
+   SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 10)), /* PG_EINT10 */ 
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11), 
+   SUNXI_FUNCTION(0x0, "gpio_in"), 
+   SUNXI_FUNCTION(0x1, "gpio_out"), 
+   SUNXI_FUNCTION(0x2, "i2s1"), /* CLK */ 
+   SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 11)), /* PG_EINT11 */ 
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12), 
+   SUNXI_FUNCTION(0x0, "gpio_in"), 
+   SUNXI_FUNCTION(0x1, "gpio_out"), 
+   SUNXI_FUNCTION(0x2, "i2s1"), /* DOUT */ 
+   SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 12)), /* PG_EINT12 */ 
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13), 
+   SUNXI_FUNCTION(0x0, "gpio_in"), 
+   SUNXI_FUNCTION(0x1, "gpio_out"), 
+   SUNXI_FUNCTION(0x2, "i2s1"), /* DIN */ 
+   SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 13)), /* PG_EINT13 */ 
+}; 
+ 
+static const struct sunxi_pinctrl_desc sun50i_h5_pinctrl_data = { 
+ .pins = sun50i_h5_pins, 
+ .npins = ARRAY_SIZE(sun50i_h5_pins), 
+ .irq_banks = 2, 
+ .irq_read_needs_mux = true 
+}; 
+ 
+static int sun50i_h5_pinctrl_probe(struct platform_device *pdev) 
+{ 
+ return sunxi_pinctrl_init(pdev, 
+   &sun50i_h5_pinctrl_data); 
+} 
+ 
+static const struct of_device_id sun50i_h5_pinctrl_match[] = { 
+ { .compatible = "allwinner,sun50i-h5-pinctrl", }, 
+ {} 
+}; 
+ 
+static struct platform_driver sun50i_h5_pinctrl_driver = { 
+ .probe = sun50i_h5_pinctrl_probe, 
+ .driver = { 
+ .name = "sun50i-h5-pinctrl", 
+ .of_match_table = sun50i_h5_pinctrl_match, 
+ }, 
+}; 
+builtin_platform_driver(sun50i_h5_pinctrl_driver); 

This also looks very much like the H3. I'll post a patchset during the 
weekend to avoid duplicating those drivers. This was initially done 
for the sun5i, but it very much applies here. 

Maxime 

-- 
Maxime Ripard, Free Electrons 
Embedded Linux and Kernel engineering 
http://free-electrons.com 

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