[PATCH v2] arm64: dts: zx: add zx296718's topcrm node

Enable topcrm clock node for zx296718, which is used for
CPU's frequency change.

Furthermore, this patch adds the CPU clock phandle in CPU's node
and uses operating-points-v2 to register operating points.

So it can be used by cpufreq-dt driver.

Signed-off-by: Baoyou Xie <redacted>
---
 arch/arm64/boot/dts/zte/zx296718.dtsi | 43 +++++++++++++++++++++++++++++++++++
 1 file changed, 43 insertions(+)

diff --git a/arch/arm64/boot/dts/zte/zx296718.dtsi b/arch/arm64/boot/dts/zte/zx296718.dtsi
index 6b239a3..992158a 100644
--- a/arch/arm64/boot/dts/zte/zx296718.dtsi
+++ b/arch/arm64/boot/dts/zte/zx296718.dtsi

@@ -44,6 +44,7 @@
 #include <dt-bindings/input/input.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/clock/zx296718-clock.h>
 
 / {
 	compatible = "zte,zx296718";

@@ -81,6 +82,8 @@
 			compatible = "arm,cortex-a53","arm,armv8";
 			reg = <0x0 0x0>;
 			enable-method = "psci";
+			clocks = <&topcrm A53_GATE>;
+			operating-points-v2 = <&cluster0_opp>;
 		};
 
 		cpu1: cpu@1 {

@@ -88,6 +91,7 @@
 			compatible = "arm,cortex-a53","arm,armv8";
 			reg = <0x0 0x1>;
 			enable-method = "psci";
+			operating-points-v2 = <&cluster0_opp>;
 		};
 
 		cpu2: cpu@2 {

@@ -95,6 +99,7 @@
 			compatible = "arm,cortex-a53","arm,armv8";
 			reg = <0x0 0x2>;
 			enable-method = "psci";
+			operating-points-v2 = <&cluster0_opp>;
 		};
 
 		cpu3: cpu@3 {

@@ -102,6 +107,38 @@
 			compatible = "arm,cortex-a53","arm,armv8";
 			reg = <0x0 0x3>;
 			enable-method = "psci";
+			operating-points-v2 = <&cluster0_opp>;
+		};
+	};
+
+	cluster0_opp: opp_table0 {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp@500000000 {
+			opp-hz = /bits/ 64 <500000000>;
+			opp-microvolt = <857000>;
+			clock-latency-ns = <500000>;
+		};
+		opp@648000000 {
+			opp-hz = /bits/ 64 <648000000>;
+			opp-microvolt = <857000>;
+			clock-latency-ns = <500000>;
+		};
+		opp@800000000 {
+			opp-hz = /bits/ 64 <800000000>;
+			opp-microvolt = <882000>;
+			clock-latency-ns = <500000>;
+		};
+		opp@1000000000 {
+			opp-hz = /bits/ 64 <1000000000>;
+			opp-microvolt = <892000>;
+			clock-latency-ns = <500000>;
+		};
+		opp@1188000000 {
+			opp-hz = /bits/ 64 <1188000000>;
+			opp-microvolt = <1009000>;
+			clock-latency-ns = <500000>;
 		};
 	};
 

@@ -279,6 +316,12 @@
 			dma-requests = <32>;
 		};
 
+		topcrm: clock-controller@1461000 {
+			compatible = "zte,zx296718-topcrm";
+			reg = <0x01461000 0x1000>;
+			#clock-cells = <1>;
+		};
+
 		sysctrl: sysctrl@1463000 {
 			compatible = "zte,zx296718-sysctrl", "syscon";
 			reg = <0x1463000 0x1000>;

-- 
2.7.4

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2016-11-30 17:50 GMT+08:00 Baoyou Xie [off-list ref]:

Enable topcrm clock node for zx296718, which is used for
CPU's frequency change.

Please reference other device tree patches title to add a simple title
with category information. Such as
arm64: dts: uniphier: change MIO node to SD control node

Furthermore, this patch adds the CPU clock phandle in CPU's node
and uses operating-points-v2 to register operating points.

So it can be used by cpufreq-dt driver.

Detail comment should provide more information to support title. So
topcrm and cpu freq changes shall be split into two patches.

I see 1600m and 1800m for a53 clock source in clk driver. Aren't they
supported by product chip?

Top clock nodes patch is just merged into linux-next. You can prepare
your patch based on it.

https://www.spinics.net/lists/arm-kernel/msg535883.html

                sysctrl: sysctrl@1463000 {
                        compatible = "zte,zx296718-sysctrl", "syscon";
                        reg = <0x1463000 0x1000>;
--
2.7.4

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cause of topcrm node has been add by another patch(
https://www.spinics.net/lists/arm-kernel/msg535883.html)
<https://wx2.qq.com/cgi-bin/mmwebwx-bin/webwxcheckurl?requrl=https%3A%2F%2Fwww.spinics.net%2Flists%2Farm-kernel%2Fmsg535883.html&skey=%40crypt_180b6516_03c09cd122d18259116435c82637657d&deviceid=e227231113535420&pass_ticket=LcwX1HPKOyjV9bHO4rred18DfLeMWaWCRblxaVRH93blUR8NJfEP5tB259bk6RcB&opcode=2&scene=1&username=@7fde1b1ad7cef9d06704c35a39c01d2d292783bde3d0e6e10590ae244337bcc0>
so I will send another patch to support cpu-freq on zx296718.

everyone can ignore this patch.


On 1 December 2016 at 09:54, Jun Nie [off-list ref] wrote:

2016-11-30 17:50 GMT+08:00 Baoyou Xie [off-list ref]:

quoted

Enable topcrm clock node for zx296718, which is used for
CPU's frequency change.

Please reference other device tree patches title to add a simple title
with category information. Such as
arm64: dts: uniphier: change MIO node to SD control node

quoted

Furthermore, this patch adds the CPU clock phandle in CPU's node
and uses operating-points-v2 to register operating points.

So it can be used by cpufreq-dt driver.

Detail comment should provide more information to support title. So
topcrm and cpu freq changes shall be split into two patches.

quoted

Signed-off-by: Baoyou Xie <redacted>
---
 arch/arm64/boot/dts/zte/zx296718.dtsi | 43

+++++++++++++++++++++++++++++++++++

quoted

 1 file changed, 43 insertions(+)

diff --git a/arch/arm64/boot/dts/zte/zx296718.dtsi

b/arch/arm64/boot/dts/zte/zx296718.dtsi

quoted

index 6b239a3..992158a 100644

--- a/arch/arm64/boot/dts/zte/zx296718.dtsi
+++ b/arch/arm64/boot/dts/zte/zx296718.dtsi

@@ -44,6 +44,7 @@
 #include <dt-bindings/input/input.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/clock/zx296718-clock.h>

 / {
        compatible = "zte,zx296718";

@@ -81,6 +82,8 @@
                        compatible = "arm,cortex-a53","arm,armv8";
                        reg = <0x0 0x0>;
                        enable-method = "psci";
+                       clocks = <&topcrm A53_GATE>;
+                       operating-points-v2 = <&cluster0_opp>;
                };

                cpu1: cpu@1 {

@@ -88,6 +91,7 @@
                        compatible = "arm,cortex-a53","arm,armv8";
                        reg = <0x0 0x1>;
                        enable-method = "psci";
+                       operating-points-v2 = <&cluster0_opp>;
                };

                cpu2: cpu@2 {

@@ -95,6 +99,7 @@
                        compatible = "arm,cortex-a53","arm,armv8";
                        reg = <0x0 0x2>;
                        enable-method = "psci";
+                       operating-points-v2 = <&cluster0_opp>;
                };

                cpu3: cpu@3 {

@@ -102,6 +107,38 @@
                        compatible = "arm,cortex-a53","arm,armv8";
                        reg = <0x0 0x3>;
                        enable-method = "psci";
+                       operating-points-v2 = <&cluster0_opp>;
+               };
+       };
+
+       cluster0_opp: opp_table0 {
+               compatible = "operating-points-v2";
+               opp-shared;
+
+               opp@500000000 {
+                       opp-hz = /bits/ 64 <500000000>;
+                       opp-microvolt = <857000>;
+                       clock-latency-ns = <500000>;
+               };
+               opp@648000000 {
+                       opp-hz = /bits/ 64 <648000000>;
+                       opp-microvolt = <857000>;
+                       clock-latency-ns = <500000>;
+               };
+               opp@800000000 {
+                       opp-hz = /bits/ 64 <800000000>;
+                       opp-microvolt = <882000>;
+                       clock-latency-ns = <500000>;
+               };
+               opp@1000000000 {
+                       opp-hz = /bits/ 64 <1000000000>;
+                       opp-microvolt = <892000>;
+                       clock-latency-ns = <500000>;
+               };
+               opp@1188000000 {
+                       opp-hz = /bits/ 64 <1188000000>;
+                       opp-microvolt = <1009000>;
+                       clock-latency-ns = <500000>;
                };

I see 1600m and 1800m for a53 clock source in clk driver. Aren't they
supported by product chip?

quoted

        };

@@ -279,6 +316,12 @@
                        dma-requests = <32>;
                };

+               topcrm: clock-controller@1461000 {
+                       compatible = "zte,zx296718-topcrm";
+                       reg = <0x01461000 0x1000>;
+                       #clock-cells = <1>;
+               };
+

Top clock nodes patch is just merged into linux-next. You can prepare
your patch based on it.

https://www.spinics.net/lists/arm-kernel/msg535883.html

quoted

                sysctrl: sysctrl@1463000 {
                        compatible = "zte,zx296718-sysctrl", "syscon";
                        reg = <0x1463000 0x1000>;
--
2.7.4