[PATCH 1/2] dt-bindings: add bindings doc for ZTE VOU display controller

@@ -0,0 +1,67 @@
+ZTE VOU Display Controller
+
+This is a display controller found on ZTE ZX296718 SoC.  It includes multiple
+Graphic Layer (GL) and Video Layer (VL), two Mixers/Channels, and a few blocks
+handling scaling, color space conversion etc.  VOU also integrates the support
+for typical output devices, like HDMI, TV Encoder, VGA, and RGB LCD.
+
+* Master display-subsystem node
+
+It must be the parent node of all the sub-device nodes.
+
+Required properties:
+ - compatible: should be "zte,zx-display-subsystem"
+ - #address-cells: should be <1>
+ - #size-cells: should be <1>
+ - ranges: to allow probing of sub-devices
+
+* VOU controller device
+
+Required properties:
+ - compatible: should be "zte,zx296718-vou"
+ - reg: Physical base address and length of the whole VOU IO region
+ - interrupts: VOU interrupt number to the CPU
+ - clocks: A list of phandle + clock-specifier pairs, one for each entry
+   in 'clock-names'
+ - clock-names: A list of clock names.  It should contain: "aclk", "ppu_wclk",
+   "main_wclk" and "aux_wclk".
+
+* HDMI output device
+
+Required properties:
+ - compatible: should be "zte,zx296718-hdmi"
+ - reg: Physical base address and length of the HDMI device IO region
+ - interrupts : HDMI interrupt number to the CPU
+ - clocks: A list of phandle + clock-specifier pairs, one for each entry
+   in 'clock-names'
+ - clock-names: A list of clock names.  It should contain: "osc_cec", "osc_clk"
+   and "xclk".
+
+Example:
+
+display-subsystem {
+	compatible = "zte,zx-display-subsystem";
+	#address-cells = <1>;
+	#size-cells = <1>;
+	ranges;
+
+	vou: vou@1440000 {
+		compatible = "zte,zx296718-vou";
+		reg = <0x1440000 0x10000>;
+		interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&topcrm VOU_ACLK>, <&topcrm VOU_PPU_WCLK>,
+			 <&topcrm VOU_MAIN_WCLK>, <&topcrm VOU_AUX_WCLK>;
+		clock-names = "aclk", "ppu_wclk",
+			      "main_wclk", "aux_wclk";
+	};
+
+	hdmi: hdmi@144c000 {
+		compatible = "zte,zx296718-hdmi";
+		reg = <0x144c000 0x4000>;
+		interrupts = <GIC_SPI 82 IRQ_TYPE_EDGE_RISING>;
+		clocks = <&topcrm HDMI_OSC_CEC>,
+			 <&topcrm HDMI_OSC_CLK>,
+			 <&topcrm HDMI_XCLK>;
+		clock-names = "osc_cec", "osc_clk", "xclk";
+	};
+};