On Tue, Aug 30, 2016 at 9:54 AM, Andrew Jeffery [off-list ref] wrote:

From: Joel Stanley <joel@jms.id.au>

The Aspeed SoCs contain GPIOs banked by letter, where each bank contains
8 pins. The GPIO banks are then grouped in sets of four in the register
layout.

The implementation exposes multiple banks through the one driver and
requests and releases pins via the pinctrl subsystem. The hardware
supports generation of interrupts from all GPIO-capable pins.

A number of hardware features are not yet supported: Configuration of
interrupt direction (ARM or LPC), debouncing, and WDT reset tolerance
for output ports.

Signed-off-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Alistair Popple <redacted>
Signed-off-by: Jeremy Kerr <jk@ozlabs.org>
Signed-off-by: Andrew Jeffery <redacted>

Patch applied to the GPIO tree.

As there are no compile-time dependencies between the
pin control and GPIO drivers I choose to merge the pinctrl
stuff through the pinctrl tree and the GPIO stuff through the GPIO
tree.

Yours,
Linus Walleij