[PATCH v3 00/13] arm/tegra: Initialize GPIO & pinmux from DT

@@ -6,3 +6,23 @@ Required properties:
   second cell is used to specify optional parameters:
   - bit 0 specifies polarity (0 for normal, 1 for inverted)
 - gpio-controller : Marks the device node as a GPIO controller.
+
+Optional properties:
+- nvidia,enabled-gpios : The list of GPIOs that should be controlled by the
+  GPIO controller rather than the pinmux controller.
+
+Example of a gpio-controller node:
+
+	gpio: gpio@6000d000 {
+		compatible = "nvidia,tegra20-gpio";
+		reg = < 0x6000d000 0x1000 >;
+		interrupts = < 64 65 66 67 87 119 121 >;
+		#gpio-cells = <2>;
+		gpio-controller;
+		nvidia,enabled-gpios = <
+			69	// TEGRA_GPIO_PI5 SD2_CD
+			57	// TEGRA_GPIO_PH1 SD2_WP
+			155	// TEGRA_GPIO_PT3 SD2_POWER
+		>;
+	};
+

@@ -0,0 +1,302 @@
+NVIDIA Tegra 2 pinmux controller
+
+Required properties:
+- compatible : "nvidia,tegra20-pinmux"
+
+Optional sub-nodes:
+- nvidia,mux-groups : Mux group settings; see below.
+- nvidia,drive-groups : Drive group settings; see below.
+
+nvidia,mux-groups sub-node:
+
+Each desired configuration of a pin group, or a set of pin groups, should be
+represented as a sub-node of the nvidia,mux-groups node. The name of the
+sub-node has no meaning.
+
+Required subnode-properties:
+- pins : An array of strings. Each string contains the name of a mux pingroup.
+    Valid values for pingroup names are listed below.
+- function : A string containing the name of the pinmux function to mux to the
+  pingroup. Valid values for function names are listed below. See the Tegra
+  TRM to determine which are valid for each pingroup:
+
+Valid pin group names for muxing are:
+
+	ata
+	atb
+	atc
+	atd
+	ate
+	cdev1
+	cdev2
+	crtp
+	csus
+	dap1
+	dap2
+	dap3
+	dap4
+	ddc
+	dta
+	dtb
+	dtc
+	dtd
+	dte
+	dtf
+	gma
+	gmb
+	gmc
+	gmd
+	gme
+	gpu
+	gpu7
+	gpv
+	hdint
+	i2cp
+	irrx
+	irtx
+	kbca
+	kbcb
+	kbcc
+	kbcd
+	kbce
+	kbcf
+	lcsn
+	ld0
+	ld1
+	ld10
+	ld11
+	ld12
+	ld13
+	ld14
+	ld15
+	ld16
+	ld17
+	ld2
+	ld3
+	ld4
+	ld5
+	ld6
+	ld7
+	ld8
+	ld9
+	ldc
+	ldi
+	lhp0
+	lhp1
+	lhp2
+	lhs
+	lm0
+	lm1
+	lpp
+	lpw0
+	lpw1
+	lpw2
+	lsc0
+	lsc1
+	lsck
+	lsda
+	lsdi
+	lspi
+	lvp0
+	lvp1
+	lvs
+	owc
+	pmc
+	pta
+	rm
+	sdb
+	sdc
+	sdd
+	sdio1
+	slxa
+	slxc
+	slxd
+	slxk
+	spdi
+	spdo
+	spia
+	spib
+	spic
+	spid
+	spie
+	spif
+	spig
+	spih
+	uaa
+	uab
+	uac
+	uad
+	uca
+	ucb
+	uda
+	ck32
+	ddrc
+	pmca
+	pmcb
+	pmcc
+	pmcd
+	pmce
+	xm2c
+	xm2d
+
+Valid function names are:
+
+	none (used for pingroups without muxing functionality)
+	ahb_clk
+	apb_clk
+	audio_sync
+	crt
+	dap1
+	dap2
+	dap3
+	dap4
+	dap5
+	displaya
+	displayb
+	emc_test0_dll
+	emc_test1_dll
+	gmi
+	gmi_int
+	hdmi
+	i2c
+	i2c2
+	i2c3
+	ide
+	irda
+	kbc
+	mio
+	mipi_hs
+	nand
+	osc
+	owr
+	pcie
+	plla_out
+	pllc_out1
+	pllm_out1
+	pllp_out2
+	pllp_out3
+	pllp_out4
+	pwm
+	pwr_intr
+	pwr_on
+	rtck
+	sdio1
+	sdio2
+	sdio3
+	sdio4
+	sflash
+	spdif
+	spi1
+	spi2
+	spi2_alt
+	spi3
+	spi4
+	trace
+	twc
+	uarta
+	uartb
+	uartc
+	uartd
+	uarte
+	ulpi
+	vi
+	vi_sensor_clk
+	xio
+
+Optional subnode-properties:
+- pull-up : Boolean, apply Tegra's internal pull-up to the pin.
+- pull-down : Boolean, apply Tegra's internal pull-down to the pin.
+- tristate : Boolean, tristate the pin. Otherwise, drive it.
+
+If both pull-up and pull-down are specified, pull-up takes precedence.
+
+nvidia,drive-groups sub-node:
+
+Each desired configuration of a pin group, or a set of pin groups, should be
+represented as a sub-node of the nvidia,drive-groups node. The name of the
+sub-node has no meaning.
+
+Required subnode-properties:
+- pins : An array of strings. Each string contains the name of a mux pingroup.
+    Valid values for pingroup names are listed below.
+- nvidia,high-speed-mode : Boolean, enable high speed mode the pins.
+- nvidia,schmitt : Boolean, enables Schmitt Trigger on the input.
+- nvidia,drive-power : Integer, valid values 0-3. 0 is least power, 3 is
+    most power. Controls the drive power or current. See "Low Power Mode"
+    or "LPMD1" and "LPMD0" in the Tegra TRM.
+- nvidia,pull-down-strength : Integer, valid values 0-31. Controls drive
+    strength. See "CAL_DRVDN" in the Tegra TRM.
+- nvidia,pull-up-strength : Integer, valid values 0-31. Controls drive
+    strength. See "CAL_DRVUP" in the Tegra TRM.
+- nvidia,slew_rate-rising : Integer, valid values 0-3. 0 is fastest, 3 is
+    slowest. See "DRVUP_SLWR" in the Tegra TRM.
+- nvidia,slew_rate-falling : Integer, valid values 0-3. 0 is fastest, 3 is
+    slowest. See "DRVDN_SLWR" in the Tegra TRM.
+
+Valid pin group names for drive configuration are:
+
+	ao1
+	ao2
+	at1
+	at2
+	cdev1
+	cdev2
+	csus
+	dap1
+	dap2
+	dap3
+	dap4
+	dbg
+	lcd1
+	lcd2
+	sdmmc2
+	sdmmc3
+	spi
+	uaa
+	uab
+	uart2
+	uart3
+	vi1
+	vi2
+	xm2a
+	xm2c
+	xm2d
+	xm2clk
+	memcomp
+	sdio1
+	crt
+	ddc
+	gma
+	gmb
+	gmc
+	gmd
+	gme
+	owr
+	uad
+
+Example of a pinmux-controller node:
+
+	pinmux: pinmux@70000000 {
+		compatible = "nvidia,tegra20-pinmux";
+		reg = < 0x70000000 0xc00 >;
+		nvidia,mux-groups {
+			lcsn {
+				pins = "lcsn", "ldc", "lm1", "lpw1", "lsc1";
+				function = "displaya";
+				pull-up;
+				tristate;
+			};
+		};
+		nvidia,drive-groups {
+			sdio1 {
+				pins = "sdio1";
+				nvidia,schmitt;
+				nvidia,drive-power = <1>;
+				nvidia,pull-down-strength = <31>;
+				nvidia,pull-up-strength = <31>;
+				nvidia,slew-rate-rising = <3>;
+				nvidia,slew-rate-falling = <3>;
+			};
+		};
+	};
+

@@ -242,6 +242,16 @@ static inline bool of_have_populated_dt(void)
 	return false;
 }
 
+#define for_each_child_of_node(parent, child) \
+	while (0)
+
+static inline struct property *of_find_property(const struct device_node *np,
+						const char *name,
+						int *lenp)
+{
+	return NULL;
+}
+
 static inline int of_property_read_u32_array(const struct device_node *np,
 					     const char *propname,
 					     u32 *out_values, size_t sz)

@@ -20,6 +20,7 @@
 #include <linux/errno.h>
 #include <linux/spinlock.h>
 #include <linux/io.h>
+#include <linux/platform_device.h>
 
 #include <mach/iomap.h>
 #include <mach/pinmux.h>

@@ -665,6 +666,25 @@ void tegra_pinmux_config_pullupdown_table(const struct tegra_pingroup_config *co
 	}
 }
 
+static int __init tegra_pinmux_probe(struct platform_device *pdev)
+{
+	return 0;
+}
+
+static struct platform_driver tegra_pinmux_driver = {
+	.driver		= {
+		.name	= "tegra-pinmux",
+		.owner	= THIS_MODULE,
+	},
+	.probe		= tegra_pinmux_probe,
+};
+
+static int __init tegra_pinmux_init(void)
+{
+	return platform_driver_register(&tegra_pinmux_driver);
+}
+postcore_initcall(tegra_pinmux_init);
+
 #ifdef	CONFIG_DEBUG_FS
 
 #include <linux/debugfs.h>

@@ -326,7 +326,6 @@ static struct irq_chip tegra_gpio_irq_chip = {
 #endif
 };
 
-
 /* This lock class tells lockdep that GPIO irqs are in a different
  * category than their parents, so it won't report false recursion.
  */

@@ -371,13 +370,35 @@ static int __init tegra_gpio_probe(struct platform_device *pdev)
 			spin_lock_init(&bank->lvl_lock[j]);
 	}
 
+	if (pdev->dev.of_node != NULL) {
+		const __be32 *gpios;
+		u32 gpioslen;
+
+		gpios = of_get_property(pdev->dev.of_node,
+					"nvidia,enabled-gpios", &gpioslen);
+		if (gpios != NULL) {
+			gpioslen /= sizeof(*gpios);
+			for (i = 0; i < gpioslen; i++, gpios++) {
+				u32 gpio = be32_to_cpup(gpios);
+				dev_dbg(&pdev->dev, "Enabling GPIO %d\n", gpio);
+				tegra_gpio_enable(gpio);
+			}
+		}
+	}
+
 	return 0;
 }
 
+static struct of_device_id tegra_gpio_of_match[] __devinitdata = {
+	{ .compatible = "nvidia,tegra20-gpio", },
+	{ },
+};
+
 static struct platform_driver tegra_gpio_driver = {
 	.driver		= {
 		.name	= "tegra-gpio",
 		.owner	= THIS_MODULE,
+		.of_match_table = tegra_gpio_of_match,
 	},
 	.probe		= tegra_gpio_probe,
 };

@@ -20,6 +20,9 @@
 #include <linux/errno.h>
 #include <linux/spinlock.h>
 #include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_iter_prop.h>
+#include <linux/of_pinmux.h>
 #include <linux/platform_device.h>
 
 #include <mach/iomap.h>

@@ -124,6 +127,19 @@ static const char *pingroup_name(enum tegra_pingroup pg)
 	return pingroups[pg].name;
 }
 
+static int pingroup_enum(const char *name, enum tegra_pingroup *pg_out)
+{
+	int pg;
+
+	for (pg = 0; pg < TEGRA_MAX_PINGROUP; pg++)
+		if (!strcasecmp(name, tegra_soc_pingroups[pg].name)) {
+			*pg_out = pg;
+			return 0;
+		}
+
+	return -EINVAL;
+}
+
 static const char *func_name(enum tegra_mux_func func)
 {
 	if (func == TEGRA_MUX_RSVD1)

@@ -147,6 +163,39 @@ static const char *func_name(enum tegra_mux_func func)
 	return tegra_mux_names[func];
 }
 
+static int func_enum(const char *name, enum tegra_mux_func *func_out)
+{
+	int func;
+
+	if (!strcasecmp(name, "RSVD1")) {
+		*func_out = TEGRA_MUX_RSVD1;
+		return 0;
+	}
+	if (!strcasecmp(name, "RSVD2")) {
+		*func_out = TEGRA_MUX_RSVD2;
+		return 0;
+	}
+	if (!strcasecmp(name, "RSVD3")) {
+		*func_out = TEGRA_MUX_RSVD3;
+		return 0;
+	}
+	if (!strcasecmp(name, "RSVD4")) {
+		*func_out = TEGRA_MUX_RSVD4;
+		return 0;
+	}
+	if (!strcasecmp(name, "NONE")) {
+		*func_out = TEGRA_MUX_NONE;
+		return 0;
+	}
+
+	for (func = 0; func < TEGRA_MAX_MUX; func++)
+		if (!strcasecmp(name, tegra_mux_names[func])) {
+			*func_out = func;
+			return 0;
+		}
+
+	return -EINVAL;
+}
 
 static const char *tri_name(unsigned long val)
 {

@@ -329,6 +378,20 @@ static const char *drive_pinmux_name(enum tegra_drive_pingroup pg)
 	return drive_pingroups[pg].name;
 }
 
+static int drive_pinmux_enum(const char *name,
+			     enum tegra_drive_pingroup *pg_out)
+{
+	int pg;
+
+	for (pg = 0; pg < TEGRA_MAX_DRIVE_PINGROUP; pg++)
+		if (!strcasecmp(name, drive_pingroups[pg].name)) {
+			*pg_out = pg;
+			return 0;
+		}
+
+	return -EINVAL;
+}
+
 static const char *enable_name(unsigned long val)
 {
 	return val ? "ENABLE" : "DISABLE";

@@ -666,15 +729,212 @@ void tegra_pinmux_config_pullupdown_table(const struct tegra_pingroup_config *co
 	}
 }
 
+struct tegra_pinmux_configs {
+	struct tegra_pingroup_config tcfg;
+	struct of_pinmux_cfg ocfg;
+};
+
+static int __init tegra_pinmux_dt_parse(const struct of_pinmux_ctrl *ctrl,
+					struct of_pinmux_cfg *cfg)
+{
+	struct tegra_pinmux_configs *cfgs =
+		container_of(cfg, struct tegra_pinmux_configs, ocfg);
+	struct tegra_pingroup_config *tcfg = &cfgs->tcfg;
+	struct of_pinmux_cfg *ocfg = &cfgs->ocfg;
+	int ret;
+
+	ret = func_enum(ocfg->function, &tcfg->func);
+	if (ret < 0) {
+		dev_err(ctrl->dev, "invalid function %s in node %s\n",
+			ocfg->function, ocfg->node->name);
+		return ret;
+	}
+
+	if (ocfg->flags & OF_PINMUX_PULL_UP)
+		tcfg->pupd = TEGRA_PUPD_PULL_UP;
+	else if (ocfg->flags & OF_PINMUX_PULL_DOWN)
+		tcfg->pupd = TEGRA_PUPD_PULL_DOWN;
+	else
+		tcfg->pupd = TEGRA_PUPD_NORMAL;
+
+	tcfg->tristate = (ocfg->flags & OF_PINMUX_TRISTATE) ?
+		TEGRA_TRI_TRISTATE : TEGRA_TRI_NORMAL;
+
+	return 0;
+}
+
+static int __init tegra_pinmux_dt_configure(const struct of_pinmux_ctrl *ctrl,
+					    const struct of_pinmux_cfg *cfg)
+{
+	struct tegra_pinmux_configs *cfgs =
+		container_of(cfg, struct tegra_pinmux_configs, ocfg);
+	struct tegra_pingroup_config *tcfg = &cfgs->tcfg;
+	struct of_pinmux_cfg *ocfg = &cfgs->ocfg;
+	int ret;
+
+	ret = pingroup_enum(ocfg->pin, &tcfg->pingroup);
+	if (ret < 0) {
+		dev_err(ctrl->dev, "invalid pingroup %s in node %s\n",
+			ocfg->pin, ocfg->node->name);
+		return ret;
+	}
+
+	tegra_pinmux_config_pingroup(tcfg);
+
+	return 0;
+}
+
+static void __init tegra_pinmux_parse_mux_groups(
+			struct platform_device *pdev,
+			struct device_node *mux_node)
+{
+	struct of_pinmux_ctrl tegra_pinmux_ctrl = {
+		.dev = &pdev->dev,
+		.node = mux_node,
+		.parse = tegra_pinmux_dt_parse,
+		.configure = tegra_pinmux_dt_configure,
+	};
+	struct tegra_pinmux_configs cfgs;
+
+	if (of_pinmux_parse(&tegra_pinmux_ctrl, &cfgs.ocfg))
+		pr_err("failed to parse pinmux configuration\n");
+}
+
+static void __init tegra_pinmux_parse_drive_groups(
+			struct platform_device *pdev,
+			struct device_node *drive_node)
+{
+	struct device_node *np;
+
+	for_each_child_of_node(drive_node, np) {
+		enum tegra_hsm hsm;
+		enum tegra_schmitt schmitt;
+		enum tegra_drive drive;
+		enum tegra_pull_strength pull_down;
+		enum tegra_pull_strength pull_up;
+		enum tegra_slew slew_rising;
+		enum tegra_slew slew_falling;
+		int ret;
+		bool hadpins = 0;
+		struct of_iter_string_prop iter;
+
+		if (of_find_property(np, "nvidia,high-speed-mode", NULL))
+			hsm = TEGRA_HSM_ENABLE;
+		else
+			hsm = TEGRA_HSM_DISABLE;
+
+		if (of_find_property(np, "nvidia,schmitt", NULL))
+			schmitt = TEGRA_SCHMITT_ENABLE;
+		else
+			schmitt = TEGRA_SCHMITT_DISABLE;
+
+		ret = of_property_read_u32(np, "nvidia,drive-power", &drive);
+		if (ret < 0) {
+			dev_err(&pdev->dev,
+				"no nvidia,drive-power for node %s\n",
+				np->name);
+			continue;
+		}
+
+		ret = of_property_read_u32(np, "nvidia,pull-down-strength",
+					   &pull_down);
+		if (ret < 0) {
+			dev_err(&pdev->dev,
+				"no nvidia,pull-down-strength for node %s\n",
+				np->name);
+			continue;
+		}
+
+		ret = of_property_read_u32(np, "nvidia,pull-up-strength",
+					   &pull_up);
+		if (ret < 0) {
+			dev_err(&pdev->dev,
+				"no nvidia,pull-up-strength for node %s\n",
+				np->name);
+			continue;
+		}
+
+		ret = of_property_read_u32(np, "nvidia,slew-rate-rising",
+					   &slew_rising);
+		if (ret < 0) {
+			dev_err(&pdev->dev,
+				"no nvidia,slew_rate-rising for node %s\n",
+				np->name);
+			continue;
+		}
+
+		ret = of_property_read_u32(np, "nvidia,slew-rate-falling",
+					   &slew_rising);
+		if (ret < 0) {
+			dev_err(&pdev->dev,
+				"no nvidia,slew_rate-falling for node %s\n",
+				np->name);
+			continue;
+		}
+
+		for_each_string_property_value(iter, np, "pins") {
+			enum tegra_drive_pingroup pg;
+
+			hadpins = 1;
+
+			ret = drive_pinmux_enum(iter.value, &pg);
+			if (ret < 0) {
+				dev_err(&pdev->dev,
+					"invalid pingroup %s in node %s\n",
+					iter.value, np->name);
+				continue;
+			}
+
+			dev_dbg(&pdev->dev,
+				"configure pin %s hsm %d schmitt %d drive %d "
+				"pull_down %d pull_up %d slew_r %d slew_f %d\n",
+				iter.value,
+				hsm, schmitt, drive,
+				pull_down, pull_up,
+				slew_rising, slew_falling);
+
+			tegra_drive_pinmux_config_pingroup(pg, hsm, schmitt,
+							   drive, pull_down,
+							   pull_up,
+							   slew_rising,
+							   slew_falling);
+		}
+
+		if (!hadpins)
+			dev_warn(&pdev->dev, "no pins for node %s\n",
+				 np->name);
+	}
+}
+
 static int __init tegra_pinmux_probe(struct platform_device *pdev)
 {
+	if (pdev->dev.of_node != NULL) {
+		struct device_node *node;
+
+		for_each_child_of_node(pdev->dev.of_node, node) {
+			if (!strcmp(node->name, "nvidia,mux-groups"))
+				tegra_pinmux_parse_mux_groups(pdev, node);
+			else if (!strcmp(node->name, "nvidia,drive-groups"))
+				tegra_pinmux_parse_drive_groups(pdev, node);
+			else
+				dev_err(&pdev->dev, "%s: Unknown child node\n",
+					node->name);
+		}
+	}
+
 	return 0;
 }
 
+static struct of_device_id tegra_pinmux_of_match[] __devinitdata = {
+	{ .compatible = "nvidia,tegra20-pinmux", },
+	{ },
+};
+
 static struct platform_driver tegra_pinmux_driver = {
 	.driver		= {
 		.name	= "tegra-pinmux",
 		.owner	= THIS_MODULE,
+		.of_match_table = tegra_pinmux_of_match,
 	},
 	.probe		= tegra_pinmux_probe,
 };

@@ -30,7 +30,6 @@ obj-${CONFIG_MACH_SEABOARD}             += board-seaboard.o
 obj-${CONFIG_MACH_SEABOARD}             += board-seaboard-pinmux.o
 
 obj-${CONFIG_MACH_TEGRA_DT}             += board-dt.o
-obj-${CONFIG_MACH_TEGRA_DT}             += board-harmony-pinmux.o
 
 obj-${CONFIG_MACH_TRIMSLICE}            += board-trimslice.o
 obj-${CONFIG_MACH_TRIMSLICE}            += board-trimslice-pinmux.o

@@ -41,14 +41,9 @@
 #include <mach/irqs.h>
 
 #include "board.h"
-#include "board-harmony.h"
 #include "clock.h"
 #include "devices.h"
 
-void harmony_pinmux_init(void);
-void seaboard_pinmux_init(void);
-
-
 struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = {
 	OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC1_BASE, "sdhci-tegra.0", NULL),
 	OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC2_BASE, "sdhci-tegra.1", NULL),

@@ -91,11 +86,6 @@ static void __init tegra_dt_init(void)
 
 	tegra_clk_init_from_table(tegra_dt_clk_init_table);
 
-	if (of_machine_is_compatible("nvidia,harmony"))
-		harmony_pinmux_init();
-	else if (of_machine_is_compatible("nvidia,seaboard"))
-		seaboard_pinmux_init();
-
 	/*
 	 * Finished with the static registrations now; fill in the missing
 	 * devices

@@ -0,0 +1,135 @@
+/*
+ * Copyright (c) 2011 NVIDIA Inc.
+ *
+ * Iterate over properties that store arrays.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef __OF_ITER_PROP_H__
+#define __OF_ITER_PROP_H__
+
+#include <linux/of.h>
+
+#ifdef CONFIG_OF
+struct of_iter_u32_prop {
+	const struct property *prop;
+	int len;
+	const __be32 *pvalue;
+	u32 value;
+};
+
+static inline void of_iter_u32_next(struct of_iter_u32_prop *iter)
+{
+	if (iter->len < 0)
+		return;
+
+	iter->value = be32_to_cpup(iter->pvalue++);
+	iter->len--;
+}
+
+static inline void of_iter_u32_init(struct of_iter_u32_prop *iter,
+				    const struct device_node *np,
+				    const char *name)
+{
+	iter->prop = of_find_property(np, name, &iter->len);
+	if (!iter->prop) {
+		iter->len = -1;
+		return;
+	}
+
+	iter->pvalue = iter->prop->value;
+	if (!iter->pvalue) {
+		iter->len = -1;
+		return;
+	}
+
+	iter->len /= sizeof(*iter->pvalue);
+
+	of_iter_u32_next(iter);
+}
+
+static inline bool of_iter_u32_test(struct of_iter_u32_prop *iter)
+{
+	return iter->len >= 0;
+}
+
+#define for_each_u32_property_value(iter, np, prop_name) \
+	for (of_iter_u32_init(&iter, np, prop_name); \
+	     of_iter_u32_test(&iter); \
+	     of_iter_u32_next(&iter))
+
+struct of_iter_string_prop {
+	const struct property *prop;
+	int len;
+	const char *value;
+	const char *after;
+};
+
+static inline void of_iter_string_init(struct of_iter_string_prop *iter,
+				       const struct device_node *np,
+				       const char *name)
+{
+	iter->prop = of_find_property(np, name, &iter->len);
+	if (!iter->prop) {
+		iter->value = NULL;
+		return;
+	}
+
+	iter->value = iter->prop->value;
+	if (!iter->value)
+		return;
+
+	iter->after = iter->value + iter->len;
+}
+
+static inline bool of_iter_string_test(struct of_iter_string_prop *iter)
+{
+	if (!iter->value)
+		return false;
+
+	return iter->value < iter->after;
+}
+
+static inline void of_iter_string_next(struct of_iter_string_prop *iter)
+{
+	int len;
+
+	if (!iter->value)
+		return;
+
+	len = strnlen(iter->value, iter->len);
+	iter->len -= len;
+	iter->value += len + 1;
+}
+
+#define for_each_string_property_value(iter, np, prop_name) \
+	for (of_iter_string_init(&iter, np, prop_name); \
+	     of_iter_string_test(&iter); \
+	     of_iter_string_next(&iter))
+
+#else
+struct of_iter_u32_prop {
+	u32 value;
+};
+
+#define for_each_u32_property_value(iter, np, prop_name) \
+	while (0)
+
+struct of_iter_string_prop {
+	const char *value;
+};
+
+#define for_each_string_property_value(iter, np, prop_name) \
+	while (0)
+
+#endif /* CONFIG_OF */
+
+#endif /* __OF_ITER_PROP_H__ */

@@ -81,4 +81,9 @@ config OF_PCI_IRQ
 	help
 	  OpenFirmware PCI IRQ routing helpers
 
+config OF_PINMUX
+	def_bool y
+	help
+	  OpenFirmware pin multiplexing helpers
+
 endmenu # OF

@@ -11,3 +11,4 @@ obj-$(CONFIG_OF_SPI)	+= of_spi.o
 obj-$(CONFIG_OF_MDIO)	+= of_mdio.o
 obj-$(CONFIG_OF_PCI)	+= of_pci.o
 obj-$(CONFIG_OF_PCI_IRQ)  += of_pci_irq.o
+obj-$(CONFIG_OF_PINMUX) += of_pinmux.o

@@ -0,0 +1,109 @@
+/*
+ * Copyright (c) 2011 Picochip Ltd., Jamie Iles
+ * Copyright (c) 2011 NVIDIA, Inc.
+ *
+ * Generic pinmux bindings for device tree.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include <linux/device.h>
+#include <linux/errno.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/of.h>
+#include <linux/of_iter_prop.h>
+#include <linux/of_pinmux.h>
+
+/**
+ * of_pinmux_parse - configure a set of pinmux groups for a pinmux controller
+ *
+ * @controller: the controller to configure the pinmux entries for.  This
+ *	defines the controller device node and the callback for configuring
+ *	the pingroups.
+ *
+ * This helper loops over all of the child nodes of a pinmux controller and
+ * collects the configuration for each pinmux group.  A pinmux group is
+ * defined as one or more pins that are configured to a common function.  This
+ * handles common properties that many platforms may implement, but for
+ * platform specific properties these may be handled in the configure
+ * callback.
+ */
+int of_pinmux_parse(const struct of_pinmux_ctrl *ctrl,
+		    struct of_pinmux_cfg *cfg)
+{
+	struct device_node *np;
+
+	if (!ctrl || !ctrl->dev || !ctrl->node || !ctrl->configure)
+		return -EINVAL;
+
+	for_each_child_of_node(ctrl->node, np) {
+		int ret;
+		bool hadpins = 0;
+		struct of_iter_string_prop iter;
+
+		cfg->node = np;
+
+		ret = of_property_read_string(np, "function",
+					      &cfg->function);
+		if (ret < 0) {
+			dev_err(ctrl->dev, "no function for node %s\n",
+				np->name);
+			continue;
+		}
+
+		cfg->flags &= 0;
+
+		if (of_find_property(np, "pull-up", NULL))
+			cfg->flags |= OF_PINMUX_PULL_UP;
+		if (of_find_property(np, "pull-down", NULL))
+			cfg->flags |= OF_PINMUX_PULL_DOWN;
+
+		if ((cfg->flags & OF_PINMUX_PULL_MASK) ==
+		    OF_PINMUX_PULL_MASK) {
+			dev_warn(ctrl->dev, "node %s has both "
+				 "pull-up and pull-down properties - "
+				 "defaulting to no pull\n",
+				 np->name);
+			cfg->flags &= ~OF_PINMUX_PULL_MASK;
+		}
+
+		if (of_find_property(np, "tristate", NULL))
+			cfg->flags |= OF_PINMUX_TRISTATE;
+
+		if (ctrl->parse && ctrl->parse(ctrl, cfg)) {
+			dev_warn(ctrl->dev,
+				    "failed to parse node %s\n",
+				    np->name);
+			continue;
+		}
+
+		for_each_string_property_value(iter, np, "pins") {
+			hadpins = 1;
+
+			cfg->pin = iter.value;
+
+			dev_dbg(ctrl->dev,
+				"configure pin %s func=%s flags=0x%lx\n",
+				cfg->pin, cfg->function, cfg->flags);
+			if (ctrl->configure(ctrl, cfg))
+				dev_warn(ctrl->dev,
+					 "failed to configure pin %s\n",
+					 cfg->pin);
+		}
+
+		if (!hadpins)
+			dev_warn(ctrl->dev, "no pins for node %s\n",
+				 np->name);
+	}
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(of_pinmux_parse);

@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2011 Picochip Ltd., Jamie Iles
+ * Copyright (c) 2011 NVIDIA, Inc.
+ *
+ * Generic pinmux bindings for device tree.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef __OF_PINMUX_H__
+#define __OF_PINMUX_H__
+
+struct device_node;
+
+#define OF_PINMUX_PULL_UP	(1 << 0)
+#define OF_PINMUX_PULL_DOWN	(1 << 1)
+#define OF_PINMUX_TRISTATE	(1 << 2)
+
+#define OF_PINMUX_PULL_MASK	(OF_PINMUX_PULL_UP | OF_PINMUX_PULL_DOWN)
+
+/**
+ * struct of_pinmux_cfg - configuration state for a single pinmux entry.
+ *
+ * @function: the name of the function that the pinmux entry should be
+ *	configured to.
+ * @pin: the device_node of the pinmux entry that should be configured.
+ *	Platform specific properties that aren't in the generic binding may be
+ *	obtained from this device node.
+ * @flags: flags for common pinmux options such as pull and tristate.
+ */
+struct of_pinmux_cfg {
+	struct device_node	*node;
+	const char		*pin;
+	const char		*function;
+	unsigned long		flags;
+};
+
+/**
+ * struct of_pinmux_ctrl - platform specific pinmux control state.
+ *
+ * @pinmux: the pinmux device node.  All child nodes are required to be the
+ *	pinmux entry definitions.  Depending on the platform, this may either be
+ *	a single pin or a group of pins where they can be set to a common
+ *	function.
+ * @configure: platform specific callback to configure the pinmux entry.
+ */
+struct of_pinmux_ctrl {
+	struct device	   *dev;
+	struct device_node *node;
+	int		   (*parse)(const struct of_pinmux_ctrl *ctrl,
+				    struct of_pinmux_cfg *cfg);
+	int		   (*configure)(const struct of_pinmux_ctrl *ctrl,
+					const struct of_pinmux_cfg *cfg);
+};
+
+#ifdef CONFIG_OF
+extern int of_pinmux_parse(const struct of_pinmux_ctrl *ctrl,
+			   struct of_pinmux_cfg *cfg);
+#else
+static inline int of_pinmux_parse(const struct of_pinmux_ctrl *ctrl,
+				  struct of_pinmux_cfg *cfg)
+{
+	return -ENOSYS;
+}
+#endif /* CONFIG_OF */
+
+#endif /* __OF_PINMUX_H__ */

@@ -20,10 +20,10 @@
 #include <linux/init.h>
 #include <linux/irq.h>
 #include <linux/interrupt.h>
-
 #include <linux/io.h>
 #include <linux/gpio.h>
 #include <linux/of.h>
+#include <linux/platform_device.h>
 
 #include <asm/mach/irq.h>
 

@@ -332,7 +332,7 @@ static struct irq_chip tegra_gpio_irq_chip = {
  */
 static struct lock_class_key gpio_lock_class;
 
-static int __init tegra_gpio_init(void)
+static int __init tegra_gpio_probe(struct platform_device *pdev)
 {
 	struct tegra_gpio_bank *bank;
 	int gpio;

@@ -346,15 +346,6 @@ static int __init tegra_gpio_init(void)
 		}
 	}
 
-#ifdef CONFIG_OF_GPIO
-	/*
-	 * This isn't ideal, but it gets things hooked up until this
-	 * driver is converted into a platform_device
-	 */
-	tegra_gpio_chip.of_node = of_find_compatible_node(NULL, NULL,
-						"nvidia,tegra20-gpio");
-#endif /* CONFIG_OF_GPIO */
-
 	gpiochip_add(&tegra_gpio_chip);
 
 	for (gpio = 0; gpio < TEGRA_NR_GPIOS; gpio++) {

@@ -383,6 +374,18 @@ static int __init tegra_gpio_init(void)
 	return 0;
 }
 
+static struct platform_driver tegra_gpio_driver = {
+	.driver		= {
+		.name	= "tegra-gpio",
+		.owner	= THIS_MODULE,
+	},
+	.probe		= tegra_gpio_probe,
+};
+
+static int __init tegra_gpio_init(void)
+{
+	return platform_driver_register(&tegra_gpio_driver);
+}
 postcore_initcall(tegra_gpio_init);
 
 void __init tegra_gpio_config(struct tegra_gpio_table *table, int num)

@@ -30,6 +30,249 @@
 		>;
 	};
 
+	pinmux: pinmux@70000000 {
+		nvidia,mux-groups {
+			ata {
+				pins = "ata";
+				function = "ide";
+			};
+			atb {
+				pins = "atb", "gma", "gme";
+				function = "sdio4";
+			};
+			atc {
+				pins = "atc";
+				function = "nand";
+			};
+			atd {
+				pins = "atd", "ate", "gmb", "gmd", "spia", "spib";
+				function = "gmi";
+			};
+			cdev1 {
+				pins = "cdev1";
+				function = "plla_out";
+			};
+			cdev2 {
+				pins = "cdev2";
+				function = "pllp_out4";
+				pull-down;
+				tristate;
+			};
+			ck32 {
+				pins = "ck32", "ddrc", "pmca", "pmcb", "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
+				function = "none";
+			};
+			crtp {
+				pins = "crtp";
+				function = "crt";
+				tristate;
+			};
+			csus {
+				pins = "csus";
+				function = "vi_sensor_clk";
+				pull-down;
+				tristate;
+			};
+			dap1 {
+				pins = "dap1";
+				function = "dap1";
+			};
+			dap2 {
+				pins = "dap2";
+				function = "dap2";
+				tristate;
+			};
+			dap3 {
+				pins = "dap3";
+				function = "dap3";
+				tristate;
+			};
+			dap4 {
+				pins = "dap4";
+				function = "dap4";
+				tristate;
+			};
+			ddc {
+				pins = "ddc";
+				function = "i2c2";
+				pull-up;
+			};
+			dta {
+				pins = "dta", "dtd";
+				function = "sdio2";
+				pull-up;
+			};
+			dtb {
+				pins = "dtb";
+				function = "rsvd1";
+			};
+			dtc {
+				pins = "dtc", "dte";
+				function = "rsvd1";
+				tristate;
+			};
+			dtf {
+				pins = "dtf";
+				function = "i2c3";
+				tristate;
+			};
+			gmc {
+				pins = "gmc";
+				function = "uartd";
+			};
+			gpu {
+				pins = "gpu";
+				function = "gmi";
+				tristate;
+			};
+			gpu7 {
+				pins = "gpu7";
+				function = "rtck";
+			};
+			gpv {
+				pins = "gpv", "slxa", "slxk";
+				function = "pcie";
+				tristate;
+			};
+			hdint {
+				pins = "hdint";
+				function = "hdmi";
+				pull-up;
+				tristate;
+			};
+			i2cp {
+				pins = "i2cp", "rm";
+				function = "i2c";
+			};
+			irrx {
+				pins = "irrx", "irtx";
+				function = "uarta";
+				pull-up;
+				tristate;
+			};
+			kbca {
+				pins = "kbca", "kbcb", "kbcc", "kbcd", "kbce", "kbcf";
+				function = "kbc";
+				pull-up;
+			};
+			lcsn {
+				pins = "lcsn", "ldc", "lm1", "lpw1", "lsc1", "lsck", "lsda", "lsdi", "lvp0";
+				function = "displaya";
+				pull-up;
+				tristate;
+			};
+			ld0 {
+				pins = "ld0", "ld1", "ld10", "ld11", "ld12", "ld13", "ld14", "ld15", "ld16", "ld17", "ld2", "ld3", "ld4", "ld5", "ld6", "ld7", "ld8", "ld9", "ldi", "lhp0", "lhp1", "lhp2", "lpp", "lvp1";
+				function = "displaya";
+				pull-down;
+			};
+			lhs {
+				pins = "lhs", "lm0", "lpw0", "lpw2", "lsc0", "lspi", "lvs";
+				function = "displaya";
+				pull-up;
+			};
+			owc {
+				pins = "owc";
+				function = "rsvd2";
+				pull-up;
+				tristate;
+			};
+			pmc {
+				pins = "pmc";
+				function = "pwr_on";
+			};
+			pta {
+				pins = "pta";
+				function = "hdmi";
+			};
+			sdb {
+				pins = "sdb";
+				function = "pwm";
+				tristate;
+			};
+			sdc {
+				pins = "sdc";
+				function = "pwm";
+				pull-up;
+			};
+			sdd {
+				pins = "sdd";
+				function = "pwm";
+				pull-up;
+				tristate;
+			};
+			sdio1 {
+				pins = "sdio1";
+				function = "sdio1";
+				tristate;
+			};
+			slxc {
+				pins = "slxc", "slxd";
+				function = "spdif";
+				tristate;
+			};
+			spdi {
+				pins = "spdi", "spdo", "uac";
+				function = "rsvd2";
+				tristate;
+			};
+			spic {
+				pins = "spic";
+				function = "gmi";
+				pull-up;
+				tristate;
+			};
+			spid {
+				pins = "spid", "spif";
+				function = "spi1";
+				pull-down;
+				tristate;
+			};
+			spie {
+				pins = "spie";
+				function = "spi1";
+				pull-up;
+				tristate;
+			};
+			spig {
+				pins = "spig";
+				function = "spi2_alt";
+				tristate;
+			};
+			spih {
+				pins = "spih";
+				function = "spi2_alt";
+				pull-up;
+				tristate;
+			};
+			uaa {
+				pins = "uaa", "uab";
+				function = "ulpi";
+				pull-up;
+				tristate;
+			};
+			uad {
+				pins = "uad";
+				function = "irda";
+				pull-up;
+				tristate;
+			};
+			uca {
+				pins = "uca", "ucb";
+				function = "uartc";
+				pull-up;
+				tristate;
+			};
+			uda {
+				pins = "uda";
+				function = "ulpi";
+				tristate;
+			};
+		};
+		nvidia,drive-groups {
+		};
+	};
+
 	i2c@7000c000 {
 		clock-frequency = <400000>;