Re: [PATCH v18 04/20] cxl: allow Type2 drivers to map cxl component regs
From: Jonathan Cameron <jonathan.cameron@huawei.com>
Date: 2025-09-18 11:03:52
Also in:
netdev
On Thu, 18 Sep 2025 10:17:30 +0100 alejandro.lucero-palau@amd.com wrote:
From: Alejandro Lucero <redacted> Export cxl core functions for a Type2 driver being able to discover and map the device component registers. Use it in sfc driver cxl initialization. Signed-off-by: Alejandro Lucero <redacted> Reviewed-by: Dan Williams <redacted> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
quoted hunk ↗ jump to hunk
diff --git a/drivers/net/ethernet/sfc/efx_cxl.c b/drivers/net/ethernet/sfc/efx_cxl.c index 56d148318636..cdfbe546d8d8 100644 --- a/drivers/net/ethernet/sfc/efx_cxl.c +++ b/drivers/net/ethernet/sfc/efx_cxl.c@@ -5,6 +5,7 @@ * Copyright (C) 2025, Advanced Micro Devices, Inc. */ +#include <cxl/cxl.h> #include <cxl/pci.h> #include <linux/pci.h>@@ -19,6 +20,7 @@ int efx_cxl_init(struct efx_probe_data *probe_data) struct pci_dev *pci_dev = efx->pci_dev; struct efx_cxl *cxl; u16 dvsec; + int rc; probe_data->cxl_pio_initialised = false;@@ -45,6 +47,37 @@ int efx_cxl_init(struct efx_probe_data *probe_data) if (!cxl) return -ENOMEM; + rc = cxl_pci_setup_regs(pci_dev, CXL_REGLOC_RBI_COMPONENT, + &cxl->cxlds.reg_map); + if (rc) { + dev_err(&pci_dev->dev, "No component registers (err=%d)\n", rc); + return rc; + } + + if (!cxl->cxlds.reg_map.component_map.hdm_decoder.valid) { + dev_err(&pci_dev->dev, "Expected HDM component register not found\n"); + return -ENODEV; + } + + if (!cxl->cxlds.reg_map.component_map.ras.valid) + return dev_err_probe(&pci_dev->dev, -ENODEV, + "Expected RAS component register not found\n");
Why the mix of dev_err() and dev_err_probe()? I'd prefer dev_err_probe() for all these, but we definitely don't want a mix.
quoted hunk ↗ jump to hunk
+ + rc = cxl_map_component_regs(&cxl->cxlds.reg_map, + &cxl->cxlds.regs.component, + BIT(CXL_CM_CAP_CAP_ID_RAS)); + if (rc) { + dev_err(&pci_dev->dev, "Failed to map RAS capability.\n"); + return rc; + } + + /* + * Set media ready explicitly as there are neither mailbox for checking + * this state nor the CXL register involved, both not mandatory for + * type2. + */ + cxl->cxlds.media_ready = true; + probe_data->cxl = cxl; return 0;diff --git a/include/cxl/cxl.h b/include/cxl/cxl.h index 13d448686189..3b9c8cb187a3 100644 --- a/include/cxl/cxl.h +++ b/include/cxl/cxl.h
+/** + * cxl_map_component_regs - map cxl component registers + *
Why 2 blank lines?
+ * + * @map: cxl register map to update with the mappings + * @regs: cxl component registers to work with + * @map_mask: cxl component regs to map + * + * Returns integer: success (0) or error (-ENOMEM) + * + * Made public for Type2 driver support. + */ +int cxl_map_component_regs(const struct cxl_register_map *map, + struct cxl_component_regs *regs, + unsigned long map_mask); #endif /* __CXL_CXL_H__ */
struct cxl_register_map *map);