@@ -1440,10 +1440,13 @@ static int flexcan_chip_start(struct net_device *dev)flexcan_set_bittiming(dev);+/* set freeze, halt */+err=flexcan_chip_freeze(priv);+if(err)+gotoout_chip_disable;+/* MCR*-*enablefreeze-*haltnow*onlysupervisoraccess*enablewarningint*enableindividualRXmasking
@@ -1452,9 +1455,8 @@ static int flexcan_chip_start(struct net_device *dev)*/reg_mcr=priv->read(®s->mcr);reg_mcr&=~FLEXCAN_MCR_MAXMB(0xff);-reg_mcr|=FLEXCAN_MCR_FRZ|FLEXCAN_MCR_HALT|FLEXCAN_MCR_SUPV|-FLEXCAN_MCR_WRN_EN|FLEXCAN_MCR_IRMQ|FLEXCAN_MCR_IDAM_C|-FLEXCAN_MCR_MAXMB(priv->tx_mb_idx);+reg_mcr|=FLEXCAN_MCR_SUPV|FLEXCAN_MCR_WRN_EN|FLEXCAN_MCR_IRMQ|+FLEXCAN_MCR_IDAM_C|FLEXCAN_MCR_MAXMB(priv->tx_mb_idx);/* MCR*
@@ -1825,10 +1825,14 @@ static int register_flexcandev(struct net_device *dev)if(err)gotoout_chip_disable;-/* set freeze, halt and activate FIFO, restrict register access */+/* set freeze, halt */+err=flexcan_chip_freeze(priv);+if(err)+gotoout_chip_disable;++/* activate FIFO, restrict register access */reg=priv->read(®s->mcr);-reg|=FLEXCAN_MCR_FRZ|FLEXCAN_MCR_HALT|-FLEXCAN_MCR_FEN|FLEXCAN_MCR_SUPV;+reg|=FLEXCAN_MCR_FEN|FLEXCAN_MCR_SUPV;priv->write(reg,®s->mcr);/* Currently we only support newer versions of this core
Assert HALT bit to enter freeze mode, there is a premise that FRZ bit is
asserted. This patch asserts FRZ bit in flexcan_chip_freeze, although
the reset value is 1b'1. This is a prepare patch, later patch will
invoke flexcan_chip_freeze() to enter freeze mode, which polling freeze
mode acknowledge.
Fixes: b1aa1c7a2165b ("can: flexcan: fix transition from and to freeze mode in chip_{,un}freeze")
Signed-off-by: Joakim Zhang <redacted>
---
drivers/net/can/flexcan.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)