--- v7
+++ v2
@@ -1,150 +1,23 @@
-This adds base DT definition for zx297520v3 and one board that consumes it.
-
-The stock kernel does not use the armv7 timer, but it seems to work
-fine. The board has other board-specific timers that would need a driver
-and I see no reason to bother with them since the arm standard timer
-works.
+The stock kernel does not use this timer, but it seems to work fine. The
+board has other board-specific timers that would need a driver and I see
+no reason to bother with them since the arm standard timer works.
The caveat is the non-standard GIC setup needed to handle the timer's
-level-low PPI. This is the responsibility of the boot loader and
-documented in Documentation/arch/arm/zte/zx297520v3.rst.
+level-low PPI.
Signed-off-by: Stefan Dösinger <stefandoesinger@gmail.com>
+---
+ arch/arm/boot/dts/zte/zx297520v3.dtsi | 24 ++++++++++++++++++++++++
+ 1 file changed, 24 insertions(+)
----
-
-Changes in
-v6: Squash board + timer + uart patches into one
-v5: Prepend the SoC name in the device specific DTS filename.
-v4:
- Declare all uarts
- Remove the UART aliases for now. I can revisit this when I get my
- hands on a board that exposes two UARTs.
----
- MAINTAINERS | 1 +
- arch/arm/boot/dts/Makefile | 1 +
- arch/arm/boot/dts/zte/Makefile | 3 +
- arch/arm/boot/dts/zte/zx297520v3-dlink-dwr932m.dts | 22 +++++
- arch/arm/boot/dts/zte/zx297520v3.dtsi | 103 +++++++++++++++++++++
- 5 files changed, 130 insertions(+)
-
-diff --git a/MAINTAINERS b/MAINTAINERS
-index e707176c2114..6f51ba1c5ada 100644
---- a/MAINTAINERS
-+++ b/MAINTAINERS
-@@ -3775,6 +3775,7 @@ F: drivers/video/fbdev/wmt_ge_rops.*
- ARM/ZTE ZX29 SOC SUPPORT
- M: Stefan Dösinger <stefandoesinger@gmail.com>
- F: Documentation/devicetree/bindings/arm/zte.yaml
-+F: arch/arm/boot/dts/zte/
- F: arch/arm/mach-zte/
+diff --git a/arch/arm/boot/dts/zte/zx297520v3.dtsi b/arch/arm/boot/dts/zte/zx297520v3.dtsi
+index d6c71d52b26c..ecd07f3fb8b3 100644
+--- a/arch/arm/boot/dts/zte/zx297520v3.dtsi
++++ b/arch/arm/boot/dts/zte/zx297520v3.dtsi
+@@ -24,6 +24,15 @@ soc {
+ interrupt-parent = <&gic>;
+ ranges;
- ARM/ZYNQ ARCHITECTURE
-diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
-index efe38eb25301..28fba538d552 100644
---- a/arch/arm/boot/dts/Makefile
-+++ b/arch/arm/boot/dts/Makefile
-@@ -39,3 +39,4 @@ subdir-y += unisoc
- subdir-y += vt8500
- subdir-y += xen
- subdir-y += xilinx
-+subdir-y += zte
-diff --git a/arch/arm/boot/dts/zte/Makefile b/arch/arm/boot/dts/zte/Makefile
-new file mode 100644
-index 000000000000..f052cfbd636c
---- /dev/null
-+++ b/arch/arm/boot/dts/zte/Makefile
-@@ -0,0 +1,3 @@
-+# SPDX-License-Identifier: GPL-2.0-only
-+dtb-$(CONFIG_SOC_ZX297520V3) += \
-+ zx297520v3-dlink-dwr932m.dtb
-diff --git a/arch/arm/boot/dts/zte/zx297520v3-dlink-dwr932m.dts b/arch/arm/boot/dts/zte/zx297520v3-dlink-dwr932m.dts
-new file mode 100644
-index 000000000000..1700f46aba86
---- /dev/null
-+++ b/arch/arm/boot/dts/zte/zx297520v3-dlink-dwr932m.dts
-@@ -0,0 +1,22 @@
-+// SPDX-License-Identifier: GPL-2.0-only
-+/*
-+ * Copyright (c) 2026 Stefan Dösinger <stefandoesinger@gmail.com>
-+ */
-+
-+/dts-v1/;
-+
-+#include "zx297520v3.dtsi"
-+
-+/ {
-+ model = "D-Link DWR-932M";
-+ compatible = "dlink,dwr932m", "zte,zx297520v3";
-+
-+ memory@20000000 {
-+ device_type = "memory";
-+ reg = <0x20000000 0x04000000>;
-+ };
-+};
-+
-+&uart1 {
-+ status = "okay";
-+};
-diff --git a/arch/arm/boot/dts/zte/zx297520v3.dtsi b/arch/arm/boot/dts/zte/zx297520v3.dtsi
-new file mode 100644
-index 000000000000..ca65797ed926
---- /dev/null
-+++ b/arch/arm/boot/dts/zte/zx297520v3.dtsi
-@@ -0,0 +1,103 @@
-+// SPDX-License-Identifier: GPL-2.0-only
-+/*
-+ * Copyright (c) 2026 Stefan Dösinger <stefandoesinger@gmail.com>
-+ */
-+
-+#include <dt-bindings/interrupt-controller/arm-gic.h>
-+
-+/ {
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+
-+ cpus {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ cpu@0 {
-+ device_type = "cpu";
-+ compatible = "arm,cortex-a53";
-+ reg = <0>;
-+ };
-+ };
-+
-+ /* Base bus clock and default for the UART. It will be replaced once a clock driver has
-+ * been added.
-+ */
-+ uartclk: uartclk: uartclk-26000000 {
-+ #clock-cells = <0>;
-+ compatible = "fixed-clock";
-+ clock-frequency = <26000000>;
-+ };
-+
-+ timer {
-+ compatible = "arm,armv7-timer";
-+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
-+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
-+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
-+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
-+ clock-frequency = <26000000>;
-+ interrupt-parent = <&gic>;
-+ /* I don't think uboot sets CNTVOFF and the stock kernel doesn't use the
-+ * arm timer at all. Since this is a single CPU system I don't think it
-+ * really matters that the offset is random though.
-+ */
-+ arm,cpu-registers-not-fw-configured;
-+ };
-+
-+ soc {
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ compatible = "simple-bus";
-+ interrupt-parent = <&gic>;
-+ ranges;
-+
+ /* The GIC has a non-standard way of configuring ints between level-low/level
+ * high or rising edge/falling edge at 0xf2202070 and onwards. See AP_INT_MODE_BASE
+ * and AP_PPI_MODE_REG in the ZTE kernel, although the offsets in the kernel source
@@ -154,49 +27,31 @@
+ * currently rely on the boot loader to change timer IRQs to active-low for us for
+ * now.
+ */
-+ gic: interrupt-controller@f2000000 {
-+ compatible = "arm,gic-v3";
-+ interrupt-controller;
-+ #interrupt-cells = <3>;
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ reg = <0xf2000000 0x10000>,
-+ <0xf2040000 0x20000>;
+ gic: interrupt-controller@f2000000 {
+ compatible = "arm,gic-v3";
+ interrupt-controller;
+@@ -33,5 +42,20 @@ gic: interrupt-controller@f2000000 {
+ reg = <0xf2000000 0x10000>,
+ <0xf2040000 0x20000>;
+ };
++
++ timer {
++ compatible = "arm,armv7-timer";
++ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
++ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
++ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
++ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
++ clock-frequency = <26000000>;
++ interrupt-parent = <&gic>;
++ /* I don't think uboot sets CNTVOFF and the stock kernel doesn't use the
++ * arm timer at all. Since this is a single CPU system I don't think it
++ * really matters that the offset is random though.
++ */
++ arm,cpu-registers-not-fw-configured;
+ };
-+
-+ uart0: serial@131000 {
-+ compatible = "arm,primecell";
-+ arm,primecell-periphid = <0x0018c011>;
-+ reg = <0x00131000 0x1000>;
-+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&uartclk>, <&uartclk>;
-+ clock-names = "uartclk", "apb_pclk";
-+ status = "disabled";
-+ };
-+
-+ uart1: serial@1408000 {
-+ compatible = "arm,pl011", "arm,primecell";
-+ arm,primecell-periphid = <0x0018c011>;
-+ reg = <0x01408000 0x1000>;
-+ interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&uartclk>, <&uartclk>;
-+ clock-names = "uartclk", "apb_pclk";
-+ status = "disabled";
-+ };
-+
-+ uart2: serial@140d000 {
-+ compatible = "arm,primecell";
-+ arm,primecell-periphid = <0x0018c011>;
-+ reg = <0x0140d000 0x1000>;
-+ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&uartclk>, <&uartclk>;
-+ clock-names = "uartclk", "apb_pclk";
-+ status = "disabled";
-+ };
-+ };
-+};
-
+ };
+ };
--
-2.53.0
+2.52.0