--- v5
+++ v2
@@ -3,8 +3,7 @@
no reason to bother with them since the arm standard timer works.
The caveat is the non-standard GIC setup needed to handle the timer's
-level-low PPI. This is the responsibility of the boot loader and
-documented in Documentation/arch/arm/zte/zx297520v3.rst.
+level-low PPI.
Signed-off-by: Stefan Dösinger <stefandoesinger@gmail.com>
---
@@ -12,32 +11,10 @@
1 file changed, 24 insertions(+)
diff --git a/arch/arm/boot/dts/zte/zx297520v3.dtsi b/arch/arm/boot/dts/zte/zx297520v3.dtsi
-index 0fff00f910d6..903050c684cb 100644
+index d6c71d52b26c..ecd07f3fb8b3 100644
--- a/arch/arm/boot/dts/zte/zx297520v3.dtsi
+++ b/arch/arm/boot/dts/zte/zx297520v3.dtsi
-@@ -20,6 +20,21 @@ cpu@0 {
- };
- };
-
-+ timer {
-+ compatible = "arm,armv7-timer";
-+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
-+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
-+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
-+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
-+ clock-frequency = <26000000>;
-+ interrupt-parent = <&gic>;
-+ /* I don't think uboot sets CNTVOFF and the stock kernel doesn't use the
-+ * arm timer at all. Since this is a single CPU system I don't think it
-+ * really matters that the offset is random though.
-+ */
-+ arm,cpu-registers-not-fw-configured;
-+ };
-+
- soc {
- #address-cells = <1>;
- #size-cells = <1>;
-@@ -27,6 +42,15 @@ soc {
+@@ -24,6 +24,15 @@ soc {
interrupt-parent = <&gic>;
ranges;
@@ -53,8 +30,28 @@
gic: interrupt-controller@f2000000 {
compatible = "arm,gic-v3";
interrupt-controller;
-
+@@ -33,5 +42,20 @@ gic: interrupt-controller@f2000000 {
+ reg = <0xf2000000 0x10000>,
+ <0xf2040000 0x20000>;
+ };
++
++ timer {
++ compatible = "arm,armv7-timer";
++ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
++ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
++ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
++ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
++ clock-frequency = <26000000>;
++ interrupt-parent = <&gic>;
++ /* I don't think uboot sets CNTVOFF and the stock kernel doesn't use the
++ * arm timer at all. Since this is a single CPU system I don't think it
++ * really matters that the offset is random though.
++ */
++ arm,cpu-registers-not-fw-configured;
++ };
+ };
+ };
--
-2.53.0
+2.52.0