[PATCH] perf: riscv: Clear PMU pending interrupt through vendor helper

When no hardware counters are in use, the PMU overflow handler clears the
pending interrupt directly in CSR_SIP with BIT(riscv_pmu_irq_num).

For Andes PMU, riscv_pmu_irq_num is 274 and the pending bit lives in the
vendor SLIP CSR. The direct clear therefore uses an out-of-width shift and
the wrong CSR, unlike the other exits from the same handler.

Use ALT_SBI_PMU_OVF_CLEAR_PENDING() on this early return as well.

Fixes: bc969d6cc96a ("perf: RISC-V: Introduce Andes PMU to support perf event sampling")
Assisted-by: Codex:gpt-5
Signed-off-by: Pengpeng Hou <redacted>
---
 drivers/perf/riscv_pmu_sbi.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c
index 50220f7b46d9..ff95f5f13603 100644
--- a/drivers/perf/riscv_pmu_sbi.c
+++ b/drivers/perf/riscv_pmu_sbi.c

@@ -1058,6 +1058,6 @@ static irqreturn_t pmu_sbi_ovf_handler(int irq, void *dev)
 	/* Firmware counter don't support overflow yet */
 	fidx = find_first_bit(cpu_hw_evt->used_hw_ctrs, RISCV_MAX_COUNTERS);
 	if (fidx == RISCV_MAX_COUNTERS) {
-		csr_clear(CSR_SIP, BIT(riscv_pmu_irq_num));
+		ALT_SBI_PMU_OVF_CLEAR_PENDING(riscv_pmu_irq_mask);
 		return IRQ_NONE;
 	}