[PATCH v4 0/2] Add support for GPU SMMU on QCS8300

Enable GPU SMMU function on QCS8300 platform. GPU SMMU is required
for address translation in GPU device.

Signed-off-by: Pratyush Brahma <redacted>
--
Changes since v3:
- Modified the order of clock voting and properties as suggested by Konrad
- Removed dependency on clocks in commit text as change is merged in
  linux-next before current base commit

Link to v3:
https://lore.kernel.org/all/20241227105818.28516-1-quic_pbrahma@quicinc.com/

Changes since v2:
Corrected typo in cover letter to include QCS8300
Link to
v2:https://lore.kernel.org/all/20241227104651.4531-1-quic_pbrahma@quicinc.com/

Changes since v1:
Updated bindings for gpu smmu for qcs8300 as per Dmitry's comment
Link to v1:
https://lore.kernel.org/all/20241224100521.7616-1-quic_pbrahma@quicinc.com/

---
Pratyush Brahma (2):
      dt-bindings: arm-smmu: Document QCS8300 GPU SMMU
      arm64: dts: qcom: qcs8300: Add device node for  gfx_smmu

 .../devicetree/bindings/iommu/arm,smmu.yaml        |  3 +-
 arch/arm64/boot/dts/qcom/qcs8300.dtsi              | 39 ++++++++++++++++++++++
 2 files changed, 41 insertions(+), 1 deletion(-)
---
base-commit: a13f6e0f405ed0d3bcfd37c692c7d7fa3c052154
change-id: 20250131-b4-branch-gfx-smmu-b03261963064

Best regards,
-- 
Pratyush Brahma [off-list ref]

Add the compatible for Qualcomm QCS8300 GPU SMMU. Add the compatible
in the list of clocks required by the GPU SMMU and remove it from the
list of disallowed clocks.

Signed-off-by: Pratyush Brahma <redacted>
---
 Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
index 032fdc27127bffd689ffc23630c9978c4460b336..7b9d5507d6ccd6b845a57eeae59fe80ba75cc652 100644
--- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
+++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml

@@ -90,6 +90,7 @@ properties:
           - enum:
               - qcom,qcm2290-smmu-500
               - qcom,qcs615-smmu-500
+              - qcom,qcs8300-smmu-500
               - qcom,sa8255p-smmu-500
               - qcom,sa8775p-smmu-500
               - qcom,sar2130p-smmu-500

@@ -397,6 +398,7 @@ allOf:
         compatible:
           contains:
             enum:
+              - qcom,qcs8300-smmu-500
               - qcom,sa8775p-smmu-500
               - qcom,sc7280-smmu-500
               - qcom,sc8280xp-smmu-500

@@ -581,7 +583,6 @@ allOf:
               - cavium,smmu-v2
               - marvell,ap806-smmu-500
               - nvidia,smmu-500
-              - qcom,qcs8300-smmu-500
               - qcom,qdu1000-smmu-500
               - qcom,sa8255p-smmu-500
               - qcom,sc7180-smmu-500

-- 
2.34.1

On Mon, Feb 03, 2025 at 11:17:01AM +0530, Pratyush Brahma wrote:

Add the compatible for Qualcomm QCS8300 GPU SMMU. Add the compatible
in the list of clocks required by the GPU SMMU and remove it from the
list of disallowed clocks.

Signed-off-by: Pratyush Brahma <redacted>
---
 Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

Reviewed-by: Krzysztof Kozlowski <redacted>

Best regards,
Krzysztof

Add the device node for gfx smmu that is required for gpu
specific address translations.

Signed-off-by: Pratyush Brahma <redacted>
---
 arch/arm64/boot/dts/qcom/qcs8300.dtsi | 39 +++++++++++++++++++++++++++++++++++
 1 file changed, 39 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
index 4a057f7c0d9fae0ebd1b3cf3468746b382bc886b..7a8211bec139375b5aab939f123d88fca7aceff2 100644
--- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi

@@ -2674,6 +2674,45 @@ gpucc: clock-controller@3d90000 {
 			#power-domain-cells = <1>;
 		};
 
+		adreno_smmu: iommu@3da0000 {
+			compatible = "qcom,qcs8300-smmu-500", "qcom,adreno-smmu",
+				     "qcom,smmu-500", "arm,mmu-500";
+			reg = <0x0 0x3da0000 0x0 0x20000>;
+			#iommu-cells = <2>;
+			#global-interrupts = <2>;
+
+			interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>;
+
+			clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
+				 <&gpucc GPU_CC_HUB_CX_INT_CLK>,
+				 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
+				 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
+				 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
+				 <&gpucc GPU_CC_AHB_CLK>,
+				 <&gpucc GPU_CC_HUB_AON_CLK>;
+
+			 clock-names = "gcc_gpu_memnoc_gfx_clk",
+				       "gcc_gpu_snoc_dvm_gfx_clk",
+				       "gpu_cc_ahb_clk",
+				       "gpu_cc_hlos1_vote_gpu_smmu_clk",
+				       "gpu_cc_cx_gmu_clk",
+				       "gpu_cc_hub_cx_int_clk",
+				       "gpu_cc_hub_aon_clk";
+			power-domains = <&gpucc GPU_CC_CX_GDSC>;
+			dma-coherent;
+		};
+
 		pmu@9091000 {
 			compatible = "qcom,qcs8300-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
 			reg = <0x0 0x9091000 0x0 0x1000>;

-- 
2.34.1

Hi

Can someone kindly review this patch?

-- 
Thanks and Regards
Pratyush Brahma

On 10/02/2025 05:58, Pratyush Brahma wrote:

Hi

Can someone kindly review this patch?

After 7 days? Community is not working for you to make such demands.
Observe standard waiting time. Or better: Please relax, and help out by
reviewing other patches on the mailing lists in order to relieve the
burden of maintainers and move your patches higher up the list.


Best regards,
Krzysztof

On 10/02/2025 12:41, Krzysztof Kozlowski wrote:

On 10/02/2025 05:58, Pratyush Brahma wrote:

quoted

Hi

Can someone kindly review this patch?

After 7 days? Community is not working for you to make such demands.
Observe standard waiting time. Or better: Please relax, and help out by
reviewing other patches on the mailing lists in order to relieve the
burden of maintainers and move your patches higher up the list.

Before you start pinging us, test your patches. That's one of the
easiest steps to get your patches reviewed or applied fast.

Best regards,
Krzysztof

On Mon, Feb 03, 2025 at 11:17:02AM +0530, Pratyush Brahma wrote:

Stray whitespace after the Tab symbol

+				       "gcc_gpu_snoc_dvm_gfx_clk",
+				       "gpu_cc_ahb_clk",
+				       "gpu_cc_hlos1_vote_gpu_smmu_clk",
+				       "gpu_cc_cx_gmu_clk",
+				       "gpu_cc_hub_cx_int_clk",
+				       "gpu_cc_hub_aon_clk";

clocks and clock-names do not match.

+			power-domains = <&gpucc GPU_CC_CX_GDSC>;
+			dma-coherent;
+		};
+
 		pmu@9091000 {
 			compatible = "qcom,qcs8300-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
 			reg = <0x0 0x9091000 0x0 0x1000>;

-- 
2.34.1

-- 
With best wishes
Dmitry

On 2/10/2025 4:31 PM, Dmitry Baryshkov wrote:

On Mon, Feb 03, 2025 at 11:17:02AM +0530, Pratyush Brahma wrote:

quoted

Add the device node for gfx smmu that is required for gpu
specific address translations.

Signed-off-by: Pratyush Brahma <redacted>
---
  arch/arm64/boot/dts/qcom/qcs8300.dtsi | 39 +++++++++++++++++++++++++++++++++++
  1 file changed, 39 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
index 4a057f7c0d9fae0ebd1b3cf3468746b382bc886b..7a8211bec139375b5aab939f123d88fca7aceff2 100644
--- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi

@@ -2674,6 +2674,45 @@ gpucc: clock-controller@3d90000 {
  			#power-domain-cells = <1>;
  		};
  
+		adreno_smmu: iommu@3da0000 {
+			compatible = "qcom,qcs8300-smmu-500", "qcom,adreno-smmu",
+				     "qcom,smmu-500", "arm,mmu-500";
+			reg = <0x0 0x3da0000 0x0 0x20000>;
+			#iommu-cells = <2>;
+			#global-interrupts = <2>;
+
+			interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>;
+
+			clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
+				 <&gpucc GPU_CC_HUB_CX_INT_CLK>,
+				 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
+				 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
+				 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
+				 <&gpucc GPU_CC_AHB_CLK>,
+				 <&gpucc GPU_CC_HUB_AON_CLK>;
+
+			 clock-names = "gcc_gpu_memnoc_gfx_clk",

Stray whitespace after the Tab symbol

quoted

+				       "gcc_gpu_snoc_dvm_gfx_clk",
+				       "gpu_cc_ahb_clk",
+				       "gpu_cc_hlos1_vote_gpu_smmu_clk",
+				       "gpu_cc_cx_gmu_clk",
+				       "gpu_cc_hub_cx_int_clk",
+				       "gpu_cc_hub_aon_clk";

clocks and clock-names do not match.

quoted

+			power-domains = <&gpucc GPU_CC_CX_GDSC>;
+			dma-coherent;
+		};
+
  		pmu@9091000 {
  			compatible = "qcom,qcs8300-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
  			reg = <0x0 0x9091000 0x0 0x1000>;

-- 
2.34.1

Thanks for checking. Will address these in next version.

-- 
Thanks and Regards
Pratyush Brahma

On Mon, Feb 03, 2025 at 11:17:00AM +0530, Pratyush Brahma wrote:

Enable GPU SMMU function on QCS8300 platform. GPU SMMU is required
for address translation in GPU device.

Signed-off-by: Pratyush Brahma <redacted>
--
Changes since v3:
- Modified the order of clock voting and properties as suggested by Konrad
- Removed dependency on clocks in commit text as change is merged in
  linux-next before current base commit

Link to v3:
https://lore.kernel.org/all/20241227105818.28516-1-quic_pbrahma@quicinc.com/

How are you sending these?

b4 diff 20250203-b4-branch-gfx-smmu-v4-0-eaa7aa762f48@quicinc.com
Grabbing thread from lore.kernel.org/all/20250203-b4-branch-gfx-smmu-v4-0-eaa7aa762f48@quicinc.com/t.mbox.gz
Checking for older revisions
Grabbing search results from lore.kernel.org
  Added from v3: 2 patches
---
Analyzing 7 messages in the thread
Preparing fake-am for v3: dt-bindings: arm-smmu: Document QCS8300 GPU SMMU
ERROR: v3 series incomplete; unable to create a fake-am range
---
Could not create fake-am range for lower series v3

Best regards,
Krzysztof

On 2/3/2025 1:03 PM, Krzysztof Kozlowski wrote:

On Mon, Feb 03, 2025 at 11:17:00AM +0530, Pratyush Brahma wrote:

quoted

Enable GPU SMMU function on QCS8300 platform. GPU SMMU is required
for address translation in GPU device.

Signed-off-by: Pratyush Brahma <redacted>
--
Changes since v3:
- Modified the order of clock voting and properties as suggested by Konrad
- Removed dependency on clocks in commit text as change is merged in
   linux-next before current base commit

Link to v3:
https://lore.kernel.org/all/20241227105818.28516-1-quic_pbrahma@quicinc.com/

How are you sending these?

b4 diff 20250203-b4-branch-gfx-smmu-v4-0-eaa7aa762f48@quicinc.com
Grabbing thread from lore.kernel.org/all/20250203-b4-branch-gfx-smmu-v4-0-eaa7aa762f48@quicinc.com/t.mbox.gz
Checking for older revisions
Grabbing search results from lore.kernel.org
   Added from v3: 2 patches
---
Analyzing 7 messages in the thread
Preparing fake-am for v3: dt-bindings: arm-smmu: Document QCS8300 GPU SMMU
ERROR: v3 series incomplete; unable to create a fake-am range
---
Could not create fake-am range for lower series v3

I have sent this version of the patch series using b4 for the first 
time, as suggested earlier [1]. The issue might be due to the previous 
version being sent
incorrectly using git send-mail. Consequently, I had to manually apply 
the previous patches after creating the b4 branch,
since "b4 prep -F" was throwing an error when trying to apply the last 
patch.

[1] 
https://lore.kernel.org/all/64ak7h5pwqinmcymas5i4xexa6bntvti7zkwfhzx7qrsmgaow3@zmn7jffcrp5f/

Best regards,
Krzysztof

-- 
Thanks and Regards
Pratyush Brahma

On 03/02/2025 09:37, Pratyush Brahma wrote:

quoted

How are you sending these?

b4 diff 20250203-b4-branch-gfx-smmu-v4-0-eaa7aa762f48@quicinc.com
Grabbing thread from lore.kernel.org/all/20250203-b4-branch-gfx-smmu-v4-0-eaa7aa762f48@quicinc.com/t.mbox.gz
Checking for older revisions
Grabbing search results from lore.kernel.org
   Added from v3: 2 patches
---
Analyzing 7 messages in the thread
Preparing fake-am for v3: dt-bindings: arm-smmu: Document QCS8300 GPU SMMU
ERROR: v3 series incomplete; unable to create a fake-am range
---
Could not create fake-am range for lower series v3

I have sent this version of the patch series using b4 for the first 
time, as suggested earlier [1]. The issue might be due to the previous 
version being sent
incorrectly using git send-mail. Consequently, I had to manually apply 
the previous patches after creating the b4 branch,
since "b4 prep -F" was throwing an error when trying to apply the last 
patch.

OK, that explains.

Best regards,
Krzysztof