Add missing pinctrl settings for PCIe 3.0 x4 clock request and wake
signals. Each component of PCIe communication have the following control
signals: PERST, WAKE, CLKREQ, and REFCLK. These signals work to generate
high-speed signals and communicate with other PCIe devices.
Used by root complex to endpoint depending on the power state.
PERST is referred to as a fundamental reset. PERST should be held low
until all the power rails in the system and the reference clock are stable.
A transition from low to high in this signal usually indicates the
beginning of link initialization.
WAKE signal is an active-low signal that is used to return the PCIe
interface to an active state when in a low-power state.
CLKREQ signal is also an active-low signal and is used to request the
reference clock.
Rename node from 'pcie3' to 'pcie30x4' to align with schematic
nomenclature.
Signed-off-by: Anand Moon <redacted>
---
v4: rebase on master, used RK_FUNC_GPIO GPIO function instead of PIN
number.
V3: use pinctrl local to board
V2: Update the commit messge to describe the changs.
use pinctl group as its pre define in pinctrl dtsi
---
.../arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 18 ++++++++++++------
1 file changed, 12 insertions(+), 6 deletions(-)
Add missing pinctrl settings for PCIe 3.0 x1 clock request and wake
signals. Each component of PCIe communication have the following control
signals: PERST, WAKE, CLKREQ, and REFCLK. These signals work to generate
high-speed signals and communicate with other PCIe devices.
Used by root complex to endpoint depending on the power state.
PERST is referred to as a fundamental reset. PERST should be held low
until all the power rails in the system and the reference clock are stable.
A transition from low to high in this signal usually indicates the
beginning of link initialization.
WAKE signal is an active-low signal that is used to return the PCIe
interface to an active state when in a low-power state.
CLKREQ signal is also an active-low signal and is used to request the
reference clock.
Rename node from 'pcie2' to 'pcie30x1' to align with schematic
nomenclature.
Signed-off-by: Anand Moon <redacted>
---
v4: rebase on master, used RK_FUNC_GPIO GPIO function instead of PIN
number.
V3: New patch.
---
.../arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 18 +++++++++++++-----
1 file changed, 13 insertions(+), 5 deletions(-)
Add missing pinctrl settings for PCIe 2.0 x1 clock request and wake
signals. Each component of PCIe communication have the following control
signals: PERST, WAKE, CLKREQ, and REFCLK. These signals work to generate
high-speed signals and communicate with other PCIe devices.
Used by root complex to endpoint depending on the power state.
PERST is referred to as a fundamental reset. PERST should be held low
until all the power rails in the system and the reference clock are stable.
A transition from low to high in this signal usually indicates the
beginning of link initialization.
WAKE signal is an active-low signal that is used to return the PCIe
interface to an active state when in a low-power state.
CLKREQ signal is also an active-low signal and is used to request the
reference clock.
Rename node from 'pcie2' to 'pcie20x1' to align with schematic
nomenclature.
Signed-off-by: Anand Moon <redacted>
---
v4: rebase on master, used RK_FUNC_GPIO GPIO function instead of PIN
number.
V3: New patch.
---
arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 14 ++++++++++----
1 file changed, 10 insertions(+), 4 deletions(-)
From: Jonas Karlman <jonas@kwiboo.se> Date: 2024-07-26 20:07:47
Hi Anand,
Sorry for no reply to your v3.
On 2024-07-26 13:00, Anand Moon wrote:
Add missing pinctrl settings for PCIe 3.0 x4 clock request and wake
signals. Each component of PCIe communication have the following control
signals: PERST, WAKE, CLKREQ, and REFCLK. These signals work to generate
high-speed signals and communicate with other PCIe devices.
Used by root complex to endpoint depending on the power state.
PERST is referred to as a fundamental reset. PERST should be held low
until all the power rails in the system and the reference clock are stable.
A transition from low to high in this signal usually indicates the
beginning of link initialization.
WAKE signal is an active-low signal that is used to return the PCIe
interface to an active state when in a low-power state.
CLKREQ signal is also an active-low signal and is used to request the
reference clock.
Rename node from 'pcie3' to 'pcie30x4' to align with schematic
nomenclature.
Signed-off-by: Anand Moon <redacted>
---
v4: rebase on master, used RK_FUNC_GPIO GPIO function instead of PIN
number.
Why this change? Only reset should use gpio function, if I am not
mistaken. Also how come you change the internal pull-up/down on these
pins?, and why do they differ for each pcie node in this series?
Please see [1] for some discussion related to these pins.
"""
The PERST is for sure should work as GPIO, and the same as WAKE;
for CLKREQ, only those board want to support L1SS need to work as
function IO,
"""
As stated earlier only the reset pin need to be muxed to GPIO function,
and that should also matches the only pin controlled with gpio in the
driver, if I am not mistaken.
[1] https://lore.kernel.org/u-boot/6de0ee14-3d85-4fda-af9d-9be7e0057dc8@rock-chips.com/
Regards,
Jonas
quoted hunk
V3: use pinctrl local to board
V2: Update the commit messge to describe the changs.
use pinctl group as its pre define in pinctrl dtsi
---
.../arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 18 ++++++++++++------
1 file changed, 12 insertions(+), 6 deletions(-)
Hello Anand,
On 2024-07-26 13:00, Anand Moon wrote:
Add missing pinctrl settings for PCIe 3.0 x4 clock request and wake
signals. Each component of PCIe communication have the following control
signals: PERST, WAKE, CLKREQ, and REFCLK. These signals work to generate
high-speed signals and communicate with other PCIe devices.
Used by root complex to endpoint depending on the power state.
PERST is referred to as a fundamental reset. PERST should be held low
until all the power rails in the system and the reference clock are stable.
A transition from low to high in this signal usually indicates the
beginning of link initialization.
WAKE signal is an active-low signal that is used to return the PCIe
interface to an active state when in a low-power state.
CLKREQ signal is also an active-low signal and is used to request the
reference clock.
Rename node from 'pcie3' to 'pcie30x4' to align with schematic
nomenclature.
I wonder why the three patches in this series cannot be squashed into
a single patch, because they target the same thing for the same board
dts file? I don't think that having these three separate patches may
help with possible regression tracking in the future, for example.
quoted hunk
Signed-off-by: Anand Moon <redacted>
---
v4: rebase on master, used RK_FUNC_GPIO GPIO function instead of PIN
number.
V3: use pinctrl local to board
V2: Update the commit messge to describe the changs.
use pinctl group as its pre define in pinctrl dtsi
---
.../arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 18 ++++++++++++------
1 file changed, 12 insertions(+), 6 deletions(-)
Hi Dragan,
On Sat, 27 Jul 2024 at 21:23, Dragan Simic [off-list ref] wrote:
Hello Anand,
On 2024-07-26 13:00, Anand Moon wrote:
quoted
Add missing pinctrl settings for PCIe 3.0 x4 clock request and wake
signals. Each component of PCIe communication have the following
control
signals: PERST, WAKE, CLKREQ, and REFCLK. These signals work to
generate
high-speed signals and communicate with other PCIe devices.
Used by root complex to endpoint depending on the power state.
PERST is referred to as a fundamental reset. PERST should be held low
until all the power rails in the system and the reference clock are
stable.
A transition from low to high in this signal usually indicates the
beginning of link initialization.
WAKE signal is an active-low signal that is used to return the PCIe
interface to an active state when in a low-power state.
CLKREQ signal is also an active-low signal and is used to request the
reference clock.
Rename node from 'pcie3' to 'pcie30x4' to align with schematic
nomenclature.
I wonder why the three patches in this series cannot be squashed into
a single patch, because they target the same thing for the same board
dts file? I don't think that having these three separate patches may
help with possible regression tracking in the future, for example.
Ok, I will merge this in a single patch.
Thanks
-Anand
Hi Jonas,
On Sat, 27 Jul 2024 at 01:37, Jonas Karlman [off-list ref] wrote:
Hi Anand,
Sorry for no reply to your v3.
On 2024-07-26 13:00, Anand Moon wrote:
quoted
Add missing pinctrl settings for PCIe 3.0 x4 clock request and wake
signals. Each component of PCIe communication have the following control
signals: PERST, WAKE, CLKREQ, and REFCLK. These signals work to generate
high-speed signals and communicate with other PCIe devices.
Used by root complex to endpoint depending on the power state.
PERST is referred to as a fundamental reset. PERST should be held low
until all the power rails in the system and the reference clock are stable.
A transition from low to high in this signal usually indicates the
beginning of link initialization.
WAKE signal is an active-low signal that is used to return the PCIe
interface to an active state when in a low-power state.
CLKREQ signal is also an active-low signal and is used to request the
reference clock.
Rename node from 'pcie3' to 'pcie30x4' to align with schematic
nomenclature.
Signed-off-by: Anand Moon <redacted>
---
v4: rebase on master, used RK_FUNC_GPIO GPIO function instead of PIN
number.
Why this change? Only reset should use gpio function, if I am not
mistaken. Also how come you change the internal pull-up/down on these
pins?, and why do they differ for each pcie node in this series?
Please see [1] for some discussion related to these pins.
I thought every board-specific dts supported GPIO function,
"""
The PERST is for sure should work as GPIO, and the same as WAKE;
for CLKREQ, only those board want to support L1SS need to work as
function IO,
"""
Ok understood.
As stated earlier only the reset pin need to be muxed to GPIO function,
and that should also matches the only pin controlled with gpio in the
driver, if I am not mistaken.