From: Michal Simek <michal.simek@amd.com> Date: 2023-12-20 10:00:48
Hi,
series is converting missing descriptions for child nodes and also
synchronizing name for power-controller discussed with Krzysztof in v1
version available here.
https://lore.kernel.org/r/fc7863a2-d3c5-47c8-9484-ef9cd6d7dd5d@linaro.org
Thanks,
Michal
Changes in v2:
- Sort nodes by name
- Rename zynqmp-power to power-controller
- Keep only single patch for easier handling as done in v1
- New patch in series
- New patch is series
- New patch is series
Michal Simek (4):
dt-bindings: firmware: xilinx: Describe missing child nodes
dt-bindings: firmware: xilinx: Sort node names (clock-controller)
dt-bindings: power: reset: xilinx: Rename node names in examples
arm64: zynqmp: Rename zynqmp-power node to power-controller
.../firmware/xilinx/xlnx,zynqmp-firmware.yaml | 49 +++++++++++++++----
.../power/reset/xlnx,zynqmp-power.yaml | 4 +-
arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 2 +-
3 files changed, 43 insertions(+), 12 deletions(-)
--
2.36.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
From: Michal Simek <michal.simek@amd.com> Date: 2023-12-20 10:00:51
Firmware node has more than fpga, aes and clock child nodes but also power,
reset, gpio, pinctrl and pcap which are not described yet.
All of them have binding in separate files but there is missing connection
to firmware node that's why describe it.
Signed-off-by: Michal Simek <michal.simek@amd.com>
---
Changes in v2:
- Sort nodes by name
- Rename zynqmp-power to power-controller
- Keep only single patch for easier handling as done in v1
.../firmware/xilinx/xlnx,zynqmp-firmware.yaml | 31 +++++++++++++++++++
1 file changed, 31 insertions(+)
@@ -41,6 +41,37 @@ properties:"#power-domain-cells":const:1+gpio:+$ref:/schemas/gpio/xlnx,zynqmp-gpio-modepin.yaml#+description:The gpio node describes connect to PS_MODE pins via firmware+interface.+type:object++pcap:+$ref:/schemas/fpga/xlnx,zynqmp-pcap-fpga.yaml+description:The ZynqMP SoC uses the PCAP (Processor Configuration Port) to+configure the Programmable Logic (PL). The configuration uses the+firmware interface.+type:object++pinctrl:+$ref:/schemas/pinctrl/xlnx,zynqmp-pinctrl.yaml#+description:The pinctrl node provides access to pinconfig and pincontrol+functionality available in firmware.+type:object++power-controller:+$ref:/schemas/power/reset/xlnx,zynqmp-power.yaml#+description:The zynqmp-power node describes the power management+configurations. It will control remote suspend/shutdown interfaces.+type:object++reset-controller:+$ref:/schemas/reset/xlnx,zynqmp-reset.yaml#+description:The reset-controller node describes connection to the reset+functionality via firmware interface.+type:object+versal-fpga:$ref:/schemas/fpga/xlnx,versal-fpga.yaml#description:Compatible of the FPGA device.
--
2.36.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
From: Michal Simek <michal.simek@amd.com> Date: 2023-12-20 10:00:59
Nodes should be sorted that's why move clock-controller to the top of list.
Signed-off-by: Michal Simek <michal.simek@amd.com>
---
Changes in v2:
- New patch in series
.../firmware/xilinx/xlnx,zynqmp-firmware.yaml | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)
@@ -41,6 +41,15 @@ properties:"#power-domain-cells":const:1+clock-controller:+$ref:/schemas/clock/xlnx,versal-clk.yaml#+description:The clock controller is a hardware block of Xilinx versal+clock tree. It reads required input clock frequencies from the devicetree+and acts as clock provider for all clock consumers of PS clocks.list of+clock specifiers which are external input clocks to the given clock+controller.+type:object+gpio:$ref:/schemas/gpio/xlnx,zynqmp-gpio-modepin.yaml#description:The gpio node describes connect to PS_MODE pins via firmware
@@ -84,15 +93,6 @@ properties:vector.type:object-clock-controller:-$ref:/schemas/clock/xlnx,versal-clk.yaml#-description:The clock controller is a hardware block of Xilinx versal-clock tree. It reads required input clock frequencies from the devicetree-and acts as clock provider for all clock consumers of PS clocks.list of-clock specifiers which are external input clocks to the given clock-controller.-type:object-required:-compatible
--
2.36.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
From: Michal Simek <michal.simek@amd.com> Date: 2023-12-20 10:01:24
Rename zynqmp-power node name to power-controller which is more aligned
with generic node name recommendation.
Signed-off-by: Michal Simek <michal.simek@amd.com>
---
Changes in v2:
- New patch is series
.../devicetree/bindings/power/reset/xlnx,zynqmp-power.yaml | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
From: Michal Simek <michal.simek@amd.com> Date: 2023-12-20 10:01:30
Rename zynqmp-power node name to power-controller which is more aligned
with generic node name recommendation.
Signed-off-by: Michal Simek <michal.simek@amd.com>
---
Changes in v2:
- New patch is series
arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
From: Rob Herring <robh@kernel.org> Date: 2023-12-20 11:35:18
On Wed, 20 Dec 2023 11:00:29 +0100, Michal Simek wrote:
Rename zynqmp-power node name to power-controller which is more aligned
with generic node name recommendation.
Signed-off-by: Michal Simek <michal.simek@amd.com>
---
Changes in v2:
- New patch is series
.../devicetree/bindings/power/reset/xlnx,zynqmp-power.yaml | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/power/reset/xlnx,zynqmp-power.example.dtb: power-controller: '#power-domain-cells' is a required property
from schema $id: http://devicetree.org/schemas/power/power-domain.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/power/reset/xlnx,zynqmp-power.example.dtb: power-controller: '#power-domain-cells' is a required property
from schema $id: http://devicetree.org/schemas/power/power-domain.yaml#
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/26aa3459310ba4624ccb5865ca32017357591e4d.1703066422.git.michal.simek@amd.com
The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
From: Krzysztof Kozlowski <hidden> Date: 2023-12-21 09:17:27
On 20/12/2023 11:00, Michal Simek wrote:
quoted hunk
+ gpio:+ $ref: /schemas/gpio/xlnx,zynqmp-gpio-modepin.yaml#+ description: The gpio node describes connect to PS_MODE pins via firmware+ interface.+ type: object++ pcap:+ $ref: /schemas/fpga/xlnx,zynqmp-pcap-fpga.yaml+ description: The ZynqMP SoC uses the PCAP (Processor Configuration Port) to+ configure the Programmable Logic (PL). The configuration uses the+ firmware interface.+ type: object++ pinctrl:+ $ref: /schemas/pinctrl/xlnx,zynqmp-pinctrl.yaml#+ description: The pinctrl node provides access to pinconfig and pincontrol+ functionality available in firmware.+ type: object++ power-controller:+ $ref: /schemas/power/reset/xlnx,zynqmp-power.yaml#
This should be "power-controller" only if it is a power domain provider.
Is it? Bot's report suggest it is not, therefore I suggested
power-management.
Also, please extend the example. The top-level example for complex
devices should be complete. Apologies for not bringing it earlier.
Best regards,
Krzysztof
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
From: Krzysztof Kozlowski <hidden> Date: 2023-12-21 09:17:41
On 20/12/2023 11:00, Michal Simek wrote:
Nodes should be sorted that's why move clock-controller to the top of list.
Signed-off-by: Michal Simek <michal.simek@amd.com>
---
Changes in v2:
Acked-by: Krzysztof Kozlowski <redacted>
Best regards,
Krzysztof
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel