From: Ravi Gunasekaran <hidden> Date: 2023-02-21 12:08:20
The following series of patches add support for the following
on J721S2 common processor board,
- USB
- SerDes
- OSPI
- PCIe
Changes from v1:
* Resolve issues with dt schema reporting
* Minor changes related to consistency on node naming and value
Changes from v2:
* Added PCIe RC + EP enablement patchsets
* Added device-id for j722s2 PCIe host in dt documentation
* Reworked SERDES + WIZ enablement patchset to use properies for clocks
defines versus entire devicetree nodes. Results in cleaner code that
doesn't break dt-schema or the driver functionality.
Changes from v3:
* Rebased changes on top of '[PATCH 00/12] TI J7x Disable Incomplete DT Nodes'
* Removed "dt-bindings: PCI: Add host mode device-id for j721s2 platform" patch and
send it own series to avoid a dependency that would hold up other patches in this
series
Changes from v4:
* Add my Signed-off-by lines to all patchsets
Changes from v5:
* Removed Cc from commit messages to reduce clutter
* Squashed changes for device tree nodes that get modified latter in the patchset
series
Changes from v6:
* Changes to ti,j721s2-wiz-10g compatible string from ti,am64-wiz-10g but
requires this series to be merged first
Ref: https://lore.kernel.org/linux-arm-kernel/20221122092203.762308-1-mranostay@ti.com/
* Removed unused pcie1_ep based on feedback
* Switch from incorrect "ti,j721e-system-controller", "syscon", "simple-mfd" compatible for
SPI node to "simple-bus"
Changes from v7:
* Fix node names as per bindings document
Changes from v8:
* Update the ti,j721e-system-controller bindings document
* Fix dtbs warnings
Changes from v9:
* Disable nodes in main.dtsi and enable them in the board
specific DT file
Aswath Govindraju (7):
arm64: dts: ti: k3-j721s2-main: Add support for USB
arm64: dts: ti: k3-j721s2-mcu-wakeup: Add support of OSPI
arm64: dts: ti: k3-j721s2-common-proc-board: Enable SERDES0
arm64: dts: ti: k3-j721s2-common-proc-board: Add USB support
arm64: dts: ti: k3-j721s2: Add support for OSPI Flashes
arm64: dts: ti: k3-j721s2-main: Add PCIe device tree node
arm64: dts: ti: k3-j721s2-common-proc-board: Enable PCIe
Matt Ranostay (1):
arm64: dts: ti: k3-j721s2-main: Add SERDES and WIZ device tree node
Ravi Gunasekaran (1):
dt-bindings: mfd: ti,j721e-system-controller: Fix mux node regex
.../mfd/ti,j721e-system-controller.yaml | 8 +-
.../dts/ti/k3-j721s2-common-proc-board.dts | 98 ++++++++++++
arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 147 ++++++++++++++++++
.../boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 47 ++++++
arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi | 43 +++++
5 files changed, 342 insertions(+), 1 deletion(-)
--
2.17.1
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From: Ravi Gunasekaran <hidden> Date: 2023-02-21 12:08:31
From: Aswath Govindraju <redacted>
Add support for single instance of USB 3.0 controller in J721S2 SoC.
Signed-off-by: Aswath Govindraju <redacted>
Signed-off-by: Matt Ranostay <redacted>
Link: https://lore.kernel.org/r/20221122101616.770050-2-mranostay@ti.com
Signed-off-by: Ravi Gunasekaran <redacted>
---
I had reviewed this patch in the v5 series [1].
Since I'm taking over upstreaming this series, I removed the self
Reviewed-by tag.
Links:
[1] - https://lore.kernel.org/all/134c28a0-2d49-549c-dc8d-0887d8fd29c3@ti.com/
arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 46 ++++++++++++++++++++++
1 file changed, 46 insertions(+)
From: Ravi Gunasekaran <hidden> Date: 2023-02-21 12:08:36
From: Aswath Govindraju <redacted>
Configure first lane to PCIe, the second lane to USB and the last two lanes
to eDP. Also, add sub-nodes to SERDES0 DT node to represent SERDES0 is
connected to PCIe.
Signed-off-by: Aswath Govindraju <redacted>
Signed-off-by: Matt Ranostay <redacted>
Link: https://lore.kernel.org/r/20221122101616.770050-5-mranostay@ti.com
Signed-off-by: Ravi Gunasekaran <redacted>
---
I had reviewed this patch in the v5 series [1].
Since I'm taking over upstreaming this series, I removed the self
Reviewed-by tag.
Links:
[1] - https://lore.kernel.org/all/71ce4ecd-2a50-c69d-28be-f1a8d769970e@ti.com/
.../dts/ti/k3-j721s2-common-proc-board.dts | 27 +++++++++++++++++++
1 file changed, 27 insertions(+)
@@ -849,6 +849,49 @@};};+pcie1_rc:pcie@2910000{+compatible="ti,j7200-pcie-host","ti,j721e-pcie-host";+reg=<0x000x029100000x000x1000>,+<0x000x029170000x000x400>,+<0x000x0d8000000x000x00800000>,+<0x000x180000000x000x00001000>;+reg-names="intd_cfg","user_cfg","reg","cfg";+interrupt-names="link_state";+interrupts=<GIC_SPI330IRQ_TYPE_EDGE_RISING>;+device_type="pci";+ti,syscon-pcie-ctrl=<&scm_conf0x074>;+max-link-speed=<3>;+num-lanes=<4>;+power-domains=<&k3_pds276TI_SCI_PD_EXCLUSIVE>;+clocks=<&k3_clks27641>;+clock-names="fck";+#address-cells=<3>;+#size-cells=<2>;+bus-range=<0x00xff>;+vendor-id=<0x104c>;+device-id=<0xb013>;+msi-map=<0x0&gic_its0x00x10000>;+dma-coherent;+ranges=<0x010000000x00x180010000x000x180010000x00x0010000>,+<0x020000000x00x180110000x000x180110000x00x7fef000>;+dma-ranges=<0x020000000x00x00x00x00x100000x0>;+#interrupt-cells=<1>;+interrupt-map-mask=<0007>;+interrupt-map=<0001&pcie1_intc0>,/* INT A */+<0002&pcie1_intc0>,/* INT B */+<0003&pcie1_intc0>,/* INT C */+<0004&pcie1_intc0>;/* INT D */++status="disabled";++pcie1_intc:interrupt-controller{+interrupt-controller;+#interrupt-cells=<1>;+interrupt-parent=<&gic500>;+interrupts=<GIC_SPI324IRQ_TYPE_EDGE_RISING>;+};+};+main_mcan0:can@2701000{compatible="bosch,m_can";reg=<0x000x027010000x000x200>,
--
2.17.1
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From: Ravi Gunasekaran <hidden> Date: 2023-02-21 12:08:46
From: Aswath Govindraju <redacted>
x1 lane PCIe slot in the common processor board is enabled and connected to
J721S2 SOM. Add PCIe DT node in common processor board to reflect the
same.
Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Signed-off-by: Aswath Govindraju <redacted>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Matt Ranostay <redacted>
Link: https://lore.kernel.org/r/20221122101616.770050-9-mranostay@ti.com
Signed-off-by: Ravi Gunasekaran <redacted>
---
arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts | 8 ++++++++
1 file changed, 8 insertions(+)
From: Ravi Gunasekaran <hidden> Date: 2023-02-21 12:08:50
From: Aswath Govindraju <redacted>
J721S2 has an OSPI NOR flash on its SOM connected the OSPI0 instance and a
QSPI NOR flash on the common processor board connected to the OSPI1
instance. Add support for the same
Signed-off-by: Aswath Govindraju <redacted>
Signed-off-by: Matt Ranostay <redacted>
Reviewed-by: Vaishnav Achath <redacted>
Link: https://lore.kernel.org/r/20221122101616.770050-7-mranostay@ti.com
Signed-off-by: Ravi Gunasekaran <redacted>
---
.../dts/ti/k3-j721s2-common-proc-board.dts | 39 +++++++++++++++++
arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi | 43 +++++++++++++++++++
2 files changed, 82 insertions(+)
From: Ravi Gunasekaran <hidden> Date: 2023-02-21 12:15:39
mux-controller nodes may not have "reg" property. Update the regex
for such nodes to resolve the dtbs warnings
Signed-off-by: Ravi Gunasekaran <redacted>
---
.../bindings/mfd/ti,j721e-system-controller.yaml | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
@@ -45,7 +45,7 @@ properties:patternProperties:# Optional children-"^mux-controller@[0-9a-f]+$":+"^mux-controller(@|-)[0-9a-f]+$":type:objectdescription:This is the SERDES lane control mux.
From: Ravi Gunasekaran <hidden> Date: 2023-02-21 12:16:23
From: Aswath Govindraju <redacted>
The board uses lane 1 of SERDES for USB. Set the mux
accordingly.
The USB controller and EVM supports super-speed for USB0
on the Type-C port. However, the SERDES has a limitation
that up to 2 protocols can be used at a time. The SERDES is
wired for PCIe, eDP and USB super-speed. It has been
chosen to use PCIe and eDP as default. So restrict
USB0 to high-speed mode.
Signed-off-by: Aswath Govindraju <redacted>
Signed-off-by: Matt Ranostay <redacted>
Link: https://lore.kernel.org/r/20221122101616.770050-6-mranostay@ti.com
Signed-off-by: Ravi Gunasekaran <redacted>
---
I had reviewed this patch in the v5 series [1].
Since I'm taking over upstreaming this series, I removed the self
Reviewed-by tag.
Links:
[1] - https://lore.kernel.org/all/96058a13-4903-2b8c-8de2-f37fdfd3672b@ti.com/
.../dts/ti/k3-j721s2-common-proc-board.dts | 24 +++++++++++++++++++
1 file changed, 24 insertions(+)
@@ -323,6 +329,24 @@};};+&usb_serdes_mux{+idle-states=<1>;/* USB0 to SERDES lane 1 */+};++&usbss0{+status="okay";+pinctrl-0=<&main_usbss0_pins_default>;+pinctrl-names="default";+ti,vbus-divider;+ti,usb2-only;+};++&usb0{+status="okay";+dr_mode="otg";+maximum-speed="high-speed";+};+&mcu_mcan0{status="okay";pinctrl-names="default";
--
2.17.1
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From: Ravi Gunasekaran <hidden> Date: 2023-02-21 12:17:06
From: Matt Ranostay <redacted>
Add dt node for the single instance of WIZ (SERDES wrapper) and
SERDES module shared by PCIe, eDP and USB.
Signed-off-by: Matt Ranostay <redacted>
Link: https://lore.kernel.org/r/20221122101616.770050-3-mranostay@ti.com
Signed-off-by: Ravi Gunasekaran <redacted>
---
I had reviewed this patch in the v7 series [1].
Since I'm taking over upstreaming this series, I removed the self
Reviewed-by tag.
Links:
[1] - https://lore.kernel.org/lkml/4173e0c6-61d9-5b79-44ec-317870de070b@ti.com/
arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 60 +++++++++++++++++++++-
1 file changed, 59 insertions(+), 1 deletion(-)
mux-controller nodes may not have "reg" property. Update the regex
for such nodes to resolve the dtbs warnings
Signed-off-by: Ravi Gunasekaran <redacted>
---
.../bindings/mfd/ti,j721e-system-controller.yaml | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
Are you expecting for me to pick this up? Looks like something
Lee Jones needs to pick up? He is'nt in the CC either?
If Lee Jones is willing to give me an immutable tag, I can pick the same
up and pick up dependent patches. Else, please split the series for each
of the maintainers to pick up without dependency.
@@ -45,7 +45,7 @@ properties:patternProperties:# Optional children-"^mux-controller@[0-9a-f]+$":+"^mux-controller(@|-)[0-9a-f]+$":type:objectdescription:This is the SERDES lane control mux.
mux-controller nodes may not have "reg" property. Update the regex
for such nodes to resolve the dtbs warnings
Signed-off-by: Ravi Gunasekaran <redacted>
---
.../bindings/mfd/ti,j721e-system-controller.yaml | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
From: Rob Herring <robh+dt@kernel.org> Date: 2023-02-21 17:04:44
On Tue, Feb 21, 2023 at 8:00 AM Vignesh Raghavendra [off-list ref] wrote:
On 21/02/23 5:36 pm, Ravi Gunasekaran wrote:
quoted
mux-controller nodes may not have "reg" property. Update the regex
for such nodes to resolve the dtbs warnings
Signed-off-by: Ravi Gunasekaran <redacted>
---
Where's the change history? I doubt I ignored the last 9 versions...
From: Ravi Gunasekaran <hidden> Date: 2023-02-22 04:33:44
On 21/02/23 7:11 pm, Nishanth Menon wrote:
On 17:36-20230221, Ravi Gunasekaran wrote:
quoted
mux-controller nodes may not have "reg" property. Update the regex
for such nodes to resolve the dtbs warnings
Signed-off-by: Ravi Gunasekaran <redacted>
---
.../bindings/mfd/ti,j721e-system-controller.yaml | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
Are you expecting for me to pick this up? Looks like something
Lee Jones needs to pick up? He is'nt in the CC either?
If Lee Jones is willing to give me an immutable tag, I can pick the same
up and pick up dependent patches. Else, please split the series for each
of the maintainers to pick up without dependency.
I apologize for the inconvenience. Based on the other review comments in this series,
I can update the mux node instead of updating the bindings document.
Regardless of it, in future I will take care of sending the patch to the right
maintainer.
@@ -45,7 +45,7 @@ properties:patternProperties:# Optional children-"^mux-controller@[0-9a-f]+$":+"^mux-controller(@|-)[0-9a-f]+$":type:objectdescription:This is the SERDES lane control mux.
From: Ravi Gunasekaran <hidden> Date: 2023-02-22 04:35:52
On 21/02/23 7:29 pm, Vignesh Raghavendra wrote:
On 21/02/23 5:36 pm, Ravi Gunasekaran wrote:
quoted
mux-controller nodes may not have "reg" property. Update the regex
for such nodes to resolve the dtbs warnings
Signed-off-by: Ravi Gunasekaran <redacted>
---
.../bindings/mfd/ti,j721e-system-controller.yaml | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
From: Ravi Gunasekaran <hidden> Date: 2023-02-22 04:38:27
On 21/02/23 10:34 pm, Rob Herring wrote:
On Tue, Feb 21, 2023 at 8:00 AM Vignesh Raghavendra [off-list ref] wrote:
quoted
On 21/02/23 5:36 pm, Ravi Gunasekaran wrote:
quoted
mux-controller nodes may not have "reg" property. Update the regex
for such nodes to resolve the dtbs warnings
Signed-off-by: Ravi Gunasekaran <redacted>
---
Where's the change history? I doubt I ignored the last 9 versions...
This change was added newly in v8.
But based on the review comments, dtbs warnings can be fixed without
changes to bindings document. So this patch will be dropped in the next
series.
Ravi
Is the link supposed to signify some reference we need to keep for ever?
No. I will remove the reference to the link. I picked up the v7 series from
previous submitter through "b4" and maintained the Link tag as-is since then.
I will remove the reference to the link in the next series.
One of the comment received in the v9 series was to disable the node in
the include file and then enable it in the board specific DTS file.
Changes in this series addressed that comment.
One of the comment received in the v9 series was to disable the node in
the include file and then enable it in the board specific DTS file.
Changes in this series addressed that comment.
Document in the node why it is disabled by default. Also do make sure
All K3 SoCs dtsi nodes follow the same argument.
--
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D
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