From: "Jason-JH.Lin" <redacted>
For previous MediaTek SoCs, such as MT8173, there are 2 display HW
pipelines binding to 1 mmsys with the same power domain, the same
clock driver and the same mediatek-drm driver.
For MT8195, VDOSYS0 and VDOSYS1 are 2 display HW pipelines binding to
2 different power domains, different clock drivers and different
mediatek-drm drivers.
Therefore, we need to separate these two different mmsys hardwares to
2 different compatibles for MT8195.
Fixes: 81c5a41d10b9 ("dt-bindings: arm: mediatek: mmsys: add mt8195 SoC binding")
Signed-off-by: Jason-JH.Lin <redacted>
Signed-off-by: Bo-Chen Chen <redacted>
---
.../devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
From: Krzysztof Kozlowski <hidden> Date: 2022-08-25 06:11:51
On 25/08/2022 08:56, Bo-Chen Chen wrote:
From: "Jason-JH.Lin" <redacted>
For previous MediaTek SoCs, such as MT8173, there are 2 display HW
pipelines binding to 1 mmsys with the same power domain, the same
clock driver and the same mediatek-drm driver.
For MT8195, VDOSYS0 and VDOSYS1 are 2 display HW pipelines binding to
2 different power domains, different clock drivers and different
mediatek-drm drivers.
I don't see binding to different clock drivers and anyway that's not
really an argument here. Please focus in description on hardware
properties, IOW, are devices compatible or different. What is the
incompatible difference between VDOSYS0 and 1?
Best regards,
Krzysztof
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
On Thu, 2022-08-25 at 14:11 +0800, Krzysztof Kozlowski wrote:
On 25/08/2022 08:56, Bo-Chen Chen wrote:
quoted
From: "Jason-JH.Lin" <redacted>
For previous MediaTek SoCs, such as MT8173, there are 2 display HW
pipelines binding to 1 mmsys with the same power domain, the same
clock driver and the same mediatek-drm driver.
For MT8195, VDOSYS0 and VDOSYS1 are 2 display HW pipelines binding
to
2 different power domains, different clock drivers and different
mediatek-drm drivers.
I don't see binding to different clock drivers and anyway that's not
really an argument here. Please focus in description on hardware
properties, IOW, are devices compatible or different. What is the
incompatible difference between VDOSYS0 and 1?
Best regards,
Krzysztof
Hello Krzysztof,
Thanks for yor review.
From the functions perspective:
Hardware pipeline of VDOSYS0 has these components: COLOR, CCORR, AAL,
GAMMA, DITHER.
They are related to PQ (Picture Quality) functions and they makes
VDOSYS0 supports PQ function while they are not including in VDOSYS1.
Hardware pipeline of VDOSYS1 has the component ETHDR (HDR related
component).
It makes VDOSYS1 supports the HDR function while it's not including in
VDOSYS0.
About mediatek ETHDR, you can refer to this series:
https://lore.kernel.org/all/20220819061456.8042-2-nancy.lin@mediatek.com/
To summary:
Only VDOSYS0 can support PQ adjustment.
Only VDOSYS1 can support HDR adjustment.
Is this description ok for you?
If it is ok, I will put them into commit message in next version.
BRs,
Bo-Chen
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
From: Krzysztof Kozlowski <hidden> Date: 2022-08-25 08:13:36
On 25/08/2022 09:59, Bo-Chen Chen wrote:
Hello Krzysztof,
Thanks for yor review.
From the functions perspective:
Hardware pipeline of VDOSYS0 has these components: COLOR, CCORR, AAL,
GAMMA, DITHER.
They are related to PQ (Picture Quality) functions and they makes
VDOSYS0 supports PQ function while they are not including in VDOSYS1.
Hardware pipeline of VDOSYS1 has the component ETHDR (HDR related
component).
It makes VDOSYS1 supports the HDR function while it's not including in
VDOSYS0.
About mediatek ETHDR, you can refer to this series:
https://lore.kernel.org/all/20220819061456.8042-2-nancy.lin@mediatek.com/
To summary:
Only VDOSYS0 can support PQ adjustment.
Only VDOSYS1 can support HDR adjustment.
Is this description ok for you?
If it is ok, I will put them into commit message in next version.
On Thu, 2022-08-25 at 14:11 +0800, Krzysztof Kozlowski wrote:
quoted
On 25/08/2022 08:56, Bo-Chen Chen wrote:
quoted
From: "Jason-JH.Lin" <redacted>
For previous MediaTek SoCs, such as MT8173, there are 2 display HW
pipelines binding to 1 mmsys with the same power domain, the same
clock driver and the same mediatek-drm driver.
For MT8195, VDOSYS0 and VDOSYS1 are 2 display HW pipelines binding
to
2 different power domains, different clock drivers and different
mediatek-drm drivers.
drop clock driver example here.
quoted
I don't see binding to different clock drivers and anyway that's not
really an argument here. Please focus in description on hardware
properties, IOW, are devices compatible or different. What is the
incompatible difference between VDOSYS0 and 1?
Best regards,
Krzysztof
Hello Krzysztof,
Thanks for yor review.
From the functions perspective:
Hardware pipeline of VDOSYS0 has these components: COLOR, CCORR, AAL,
GAMMA, DITHER.
They are related to PQ (Picture Quality) functions and they makes
VDOSYS0 supports PQ function while they are not including in VDOSYS1.
Hardware pipeline of VDOSYS1 has the component ETHDR (HDR related
component).
It makes VDOSYS1 supports the HDR function while it's not including in
VDOSYS0.
Please include a description of this in the commit message.
About mediatek ETHDR, you can refer to this series:
https://lore.kernel.org/all/20220819061456.8042-2-nancy.lin@mediatek.com/
To summary:
Only VDOSYS0 can support PQ adjustment.
Only VDOSYS1 can support HDR adjustment.
Is this description ok for you?
If it is ok, I will put them into commit message in next version.
BRs,
Bo-Chen
From: "Jason-JH.Lin" <redacted>
For previous MediaTek SoCs, such as MT8173, there are 2 display HW
pipelines binding to 1 mmsys with the same power domain, the same
clock driver and the same mediatek-drm driver.
For MT8195, VDOSYS0 and VDOSYS1 are 2 display HW pipelines binding to
2 different power domains, different clock drivers and different
mediatek-drm drivers.
Therefore, we need to separate these two different mmsys hardwares to
2 different compatibles for MT8195.
Fixes: 81c5a41d10b9 ("dt-bindings: arm: mediatek: mmsys: add mt8195 SoC binding")
Signed-off-by: Jason-JH.Lin <redacted>
Signed-off-by: Bo-Chen Chen <redacted>
---
.../devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
If I understand correctly support for vdosys0 is merged with the old compatible.
We should therefore keep mediatek,mt8195-mmsys as a fallback for
mediatek,mt8195-vdosys0.
Regards,
Matthias
On Thu, 2022-08-25 at 18:55 +0800, Matthias Brugger wrote:
On 25/08/2022 08:59, Bo-Chen Chen wrote:
quoted
On Thu, 2022-08-25 at 14:11 +0800, Krzysztof Kozlowski wrote:
quoted
On 25/08/2022 08:56, Bo-Chen Chen wrote:
quoted
From: "Jason-JH.Lin" <redacted>
For previous MediaTek SoCs, such as MT8173, there are 2 display
HW
pipelines binding to 1 mmsys with the same power domain, the
same
clock driver and the same mediatek-drm driver.
For MT8195, VDOSYS0 and VDOSYS1 are 2 display HW pipelines
binding
to
2 different power domains, different clock drivers and
different
mediatek-drm drivers.
drop clock driver example here.
Hello Matthias,
Thanks for your review.
I am not sure what do you mean.
Could you explain more detailedly?
quoted
quoted
I don't see binding to different clock drivers and anyway that's
not
really an argument here. Please focus in description on hardware
properties, IOW, are devices compatible or different. What is the
incompatible difference between VDOSYS0 and 1?
Best regards,
Krzysztof
Hello Krzysztof,
Thanks for yor review.
From the functions perspective:
Hardware pipeline of VDOSYS0 has these components: COLOR, CCORR,
AAL,
GAMMA, DITHER.
They are related to PQ (Picture Quality) functions and they makes
VDOSYS0 supports PQ function while they are not including in
VDOSYS1.
Hardware pipeline of VDOSYS1 has the component ETHDR (HDR related
component).
It makes VDOSYS1 supports the HDR function while it's not including
in
VDOSYS0.
Please include a description of this in the commit message.
To summary:
Only VDOSYS0 can support PQ adjustment.
Only VDOSYS1 can support HDR adjustment.
Is this description ok for you?
If it is ok, I will put them into commit message in next version.
BRs,
Bo-Chen
On Thu, 2022-08-25 at 18:55 +0800, Matthias Brugger wrote:
quoted
On 25/08/2022 08:59, Bo-Chen Chen wrote:
quoted
On Thu, 2022-08-25 at 14:11 +0800, Krzysztof Kozlowski wrote:
quoted
On 25/08/2022 08:56, Bo-Chen Chen wrote:
quoted
From: "Jason-JH.Lin" <redacted>
For previous MediaTek SoCs, such as MT8173, there are 2 display
HW
pipelines binding to 1 mmsys with the same power domain, the
same
clock driver and the same mediatek-drm driver.
For MT8195, VDOSYS0 and VDOSYS1 are 2 display HW pipelines
binding
to
2 different power domains, different clock drivers and
different
mediatek-drm drivers.
drop clock driver example here.
Hello Matthias,
Thanks for your review.
I am not sure what do you mean.
Could you explain more detailedly?
Never mind, it's not that important.
Regards,
Matthias
quoted
quoted
quoted
I don't see binding to different clock drivers and anyway that's
not
really an argument here. Please focus in description on hardware
properties, IOW, are devices compatible or different. What is the
incompatible difference between VDOSYS0 and 1?
Best regards,
Krzysztof
Hello Krzysztof,
Thanks for yor review.
From the functions perspective:
Hardware pipeline of VDOSYS0 has these components: COLOR, CCORR,
AAL,
GAMMA, DITHER.
They are related to PQ (Picture Quality) functions and they makes
VDOSYS0 supports PQ function while they are not including in
VDOSYS1.
Hardware pipeline of VDOSYS1 has the component ETHDR (HDR related
component).
It makes VDOSYS1 supports the HDR function while it's not including
in
VDOSYS0.
Please include a description of this in the commit message.
To summary:
Only VDOSYS0 can support PQ adjustment.
Only VDOSYS1 can support HDR adjustment.
Is this description ok for you?
If it is ok, I will put them into commit message in next version.
BRs,
Bo-Chen