[PATCH 0/3] ARM: dts: at91: enable leftover IPs

Hi,

The following series add DT nodes for TCB and RTC blocks on SAMA7G5.

Thank you,
Claudiu Beznea

Claudiu Beznea (2):
  ARM: dts: at91: sama7g5: add tcb nodes
  ARM: dts: at91: sama7g5-ek: use blocks 0 and 1 of TCB0 as cs and ce

Eugen Hristev (1):
  ARM: dts: at91: sama7g5: add rtc node

 arch/arm/boot/dts/at91-sama7g5ek.dts | 12 ++++++++++++
 arch/arm/boot/dts/sama7g5.dtsi       | 27 +++++++++++++++++++++++++++
 2 files changed, 39 insertions(+)

-- 
2.25.1


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From: Eugen Hristev <redacted>

Add RTC node.

Signed-off-by: Eugen Hristev <redacted>
[claudiu.beznea: add sama7g5 compatible as the IP has 2 extra registers
 compared with sam9x60]
Signed-off-by: Claudiu Beznea <redacted>
---
 arch/arm/boot/dts/sama7g5.dtsi | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/boot/dts/sama7g5.dtsi b/arch/arm/boot/dts/sama7g5.dtsi
index 6a9d74a9e1ac..e16a337fd100 100644
--- a/arch/arm/boot/dts/sama7g5.dtsi
+++ b/arch/arm/boot/dts/sama7g5.dtsi

@@ -152,6 +152,13 @@ gpbr: gpbr@e001d060 {
 			reg = <0xe001d060 0x48>;
 		};
 
+		rtc: rtc@e001d0a8 {
+			compatible = "microchip,sama7g5-rtc", "microchip,sam9x60-rtc";
+			reg = <0xe001d0a8 0x30>;
+			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk32k 1>;
+		};
+
 		ps_wdt: watchdog@e001d180 {
 			compatible = "microchip,sama7g5-wdt";
 			reg = <0xe001d180 0x24>;

-- 
2.25.1


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Add TCB nodes.

Signed-off-by: Claudiu Beznea <redacted>
---
 arch/arm/boot/dts/sama7g5.dtsi | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/arch/arm/boot/dts/sama7g5.dtsi b/arch/arm/boot/dts/sama7g5.dtsi
index e16a337fd100..b6ebfceaa78b 100644
--- a/arch/arm/boot/dts/sama7g5.dtsi
+++ b/arch/arm/boot/dts/sama7g5.dtsi

@@ -166,6 +166,16 @@ ps_wdt: watchdog@e001d180 {
 			clocks = <&clk32k 0>;
 		};
 
+		tcb1: timer@e0800000 {
+			compatible = "atmel,sama5d2-tcb", "simple-mfd", "syscon";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0xe0800000 0x100>;
+			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 91>, <&pmc PMC_TYPE_PERIPHERAL 92>, <&pmc PMC_TYPE_PERIPHERAL 93>, <&clk32k 1>;
+			clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
+		};
+
 		adc: adc@e1000000 {
 			compatible = "microchip,sama7g5-adc";
 			reg = <0xe1000000 0x200>;

@@ -488,6 +498,16 @@ dma2: dma-controller@e1200000 {
 			status = "disabled";
 		};
 
+		tcb0: timer@e2814000 {
+			compatible = "atmel,sama5d2-tcb", "simple-mfd", "syscon";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0xe2814000 0x100>;
+			interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 88>, <&pmc PMC_TYPE_PERIPHERAL 89>, <&pmc PMC_TYPE_PERIPHERAL 90>, <&clk32k 1>;
+			clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
+		};
+
 		flx8: flexcom@e2818000 {
 			compatible = "atmel,sama5d2-flexcom";
 			reg = <0xe2818000 0x200>;

-- 
2.25.1


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Use blocks 0 and 1 of TCB0 for clocksource and clockevent functionality.
PIT64B is already enabled on SAMA7G5 targets for this but TCB0 will be
used as a fallback only in case PIT64B will fail to probe.

Signed-off-by: Claudiu Beznea <redacted>
---
 arch/arm/boot/dts/at91-sama7g5ek.dts | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm/boot/dts/at91-sama7g5ek.dts b/arch/arm/boot/dts/at91-sama7g5ek.dts
index 0f53b2db28a2..0e1975c6812e 100644
--- a/arch/arm/boot/dts/at91-sama7g5ek.dts
+++ b/arch/arm/boot/dts/at91-sama7g5ek.dts

@@ -687,6 +687,18 @@ &spdiftx {
 	status = "okay";
 };
 
+&tcb0 {
+	timer0: timer@0 {
+		compatible = "atmel,tcb-timer";
+		reg = <0>;
+	};
+
+	timer1: timer@1 {
+		compatible = "atmel,tcb-timer";
+		reg = <1>;
+	};
+};
+
 &trng {
 	status = "okay";
 };

-- 
2.25.1


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On 20/10/2021 at 11:46, Claudiu Beznea wrote:

Hi,

The following series add DT nodes for TCB and RTC blocks on SAMA7G5.

Thank you,
Claudiu Beznea

For whole series:
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Queued in at91-dt for 5.16. I plan to send a PR tomorrow.

Best regards,
   Nicolas

Claudiu Beznea (2):
   ARM: dts: at91: sama7g5: add tcb nodes
   ARM: dts: at91: sama7g5-ek: use blocks 0 and 1 of TCB0 as cs and ce

Eugen Hristev (1):
   ARM: dts: at91: sama7g5: add rtc node

  arch/arm/boot/dts/at91-sama7g5ek.dts | 12 ++++++++++++
  arch/arm/boot/dts/sama7g5.dtsi       | 27 +++++++++++++++++++++++++++
  2 files changed, 39 insertions(+)

-- 
Nicolas Ferre

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